STM32F4xx HAL Driver master
STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_ll_fmc.c
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1
57
58/* Includes ------------------------------------------------------------------*/
59#include "stm32f4xx_hal.h"
60
64#if defined(HAL_NOR_MODULE_ENABLED) || (defined(HAL_NAND_MODULE_ENABLED)) || defined(HAL_PCCARD_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\
65 || defined(HAL_SRAM_MODULE_ENABLED)
66
71
72/* Private typedef -----------------------------------------------------------*/
73/* Private define ------------------------------------------------------------*/
74
78
79/* ----------------------- FMC registers bit mask --------------------------- */
80
81#if defined(FMC_Bank1)
82/* --- BCR Register ---*/
83/* BCR register clear mask */
84
85/* --- BTR Register ---*/
86/* BTR register clear mask */
87#define BTR_CLEAR_MASK ((uint32_t)(FMC_BTR1_ADDSET | FMC_BTR1_ADDHLD |\
88 FMC_BTR1_DATAST | FMC_BTR1_BUSTURN |\
89 FMC_BTR1_CLKDIV | FMC_BTR1_DATLAT |\
90 FMC_BTR1_ACCMOD))
91
92/* --- BWTR Register ---*/
93/* BWTR register clear mask */
94#define BWTR_CLEAR_MASK ((uint32_t)(FMC_BWTR1_ADDSET | FMC_BWTR1_ADDHLD |\
95 FMC_BWTR1_DATAST | FMC_BWTR1_BUSTURN |\
96 FMC_BWTR1_ACCMOD))
97#endif /* FMC_Bank1 */
98#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
99
100#if defined (FMC_PCR_PWAITEN)
101/* --- PCR Register ---*/
102/* PCR register clear mask */
103#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR_PWAITEN | FMC_PCR_PBKEN | \
104 FMC_PCR_PTYP | FMC_PCR_PWID | \
105 FMC_PCR_ECCEN | FMC_PCR_TCLR | \
106 FMC_PCR_TAR | FMC_PCR_ECCPS))
107/* --- PMEM Register ---*/
108/* PMEM register clear mask */
109#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM_MEMSET2 | FMC_PMEM_MEMWAIT2 |\
110 FMC_PMEM_MEMHOLD2 | FMC_PMEM_MEMHIZ2))
111
112/* --- PATT Register ---*/
113/* PATT register clear mask */
114#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT_ATTSET2 | FMC_PATT_ATTWAIT2 |\
115 FMC_PATT_ATTHOLD2 | FMC_PATT_ATTHIZ2))
116#else
117/* --- PCR Register ---*/
118/* PCR register clear mask */
119#define PCR_CLEAR_MASK ((uint32_t)(FMC_PCR2_PWAITEN | FMC_PCR2_PBKEN | \
120 FMC_PCR2_PTYP | FMC_PCR2_PWID | \
121 FMC_PCR2_ECCEN | FMC_PCR2_TCLR | \
122 FMC_PCR2_TAR | FMC_PCR2_ECCPS))
123/* --- PMEM Register ---*/
124/* PMEM register clear mask */
125#define PMEM_CLEAR_MASK ((uint32_t)(FMC_PMEM2_MEMSET2 | FMC_PMEM2_MEMWAIT2 |\
126 FMC_PMEM2_MEMHOLD2 | FMC_PMEM2_MEMHIZ2))
127
128/* --- PATT Register ---*/
129/* PATT register clear mask */
130#define PATT_CLEAR_MASK ((uint32_t)(FMC_PATT2_ATTSET2 | FMC_PATT2_ATTWAIT2 |\
131 FMC_PATT2_ATTHOLD2 | FMC_PATT2_ATTHIZ2))
132
133#endif /* FMC_PCR_PWAITEN */
134#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
135#if defined(FMC_Bank4)
136/* --- PCR Register ---*/
137/* PCR register clear mask */
138#define PCR4_CLEAR_MASK ((uint32_t)(FMC_PCR4_PWAITEN | FMC_PCR4_PBKEN | \
139 FMC_PCR4_PTYP | FMC_PCR4_PWID | \
140 FMC_PCR4_ECCEN | FMC_PCR4_TCLR | \
141 FMC_PCR4_TAR | FMC_PCR4_ECCPS))
142/* --- PMEM Register ---*/
143/* PMEM register clear mask */
144#define PMEM4_CLEAR_MASK ((uint32_t)(FMC_PMEM4_MEMSET4 | FMC_PMEM4_MEMWAIT4 |\
145 FMC_PMEM4_MEMHOLD4 | FMC_PMEM4_MEMHIZ4))
146
147/* --- PATT Register ---*/
148/* PATT register clear mask */
149#define PATT4_CLEAR_MASK ((uint32_t)(FMC_PATT4_ATTSET4 | FMC_PATT4_ATTWAIT4 |\
150 FMC_PATT4_ATTHOLD4 | FMC_PATT4_ATTHIZ4))
151
152/* --- PIO4 Register ---*/
153/* PIO4 register clear mask */
154#define PIO4_CLEAR_MASK ((uint32_t)(FMC_PIO4_IOSET4 | FMC_PIO4_IOWAIT4 | \
155 FMC_PIO4_IOHOLD4 | FMC_PIO4_IOHIZ4))
156
157#endif /* FMC_Bank4 */
158#if defined(FMC_Bank5_6)
159
160/* --- SDCR Register ---*/
161/* SDCR register clear mask */
162#define SDCR_CLEAR_MASK ((uint32_t)(FMC_SDCR1_NC | FMC_SDCR1_NR | \
163 FMC_SDCR1_MWID | FMC_SDCR1_NB | \
164 FMC_SDCR1_CAS | FMC_SDCR1_WP | \
165 FMC_SDCR1_SDCLK | FMC_SDCR1_RBURST | \
166 FMC_SDCR1_RPIPE))
167
168/* --- SDTR Register ---*/
169/* SDTR register clear mask */
170#define SDTR_CLEAR_MASK ((uint32_t)(FMC_SDTR1_TMRD | FMC_SDTR1_TXSR | \
171 FMC_SDTR1_TRAS | FMC_SDTR1_TRC | \
172 FMC_SDTR1_TWR | FMC_SDTR1_TRP | \
173 FMC_SDTR1_TRCD))
174#endif /* FMC_Bank5_6 */
175
179
180/* Private macro -------------------------------------------------------------*/
181/* Private variables ---------------------------------------------------------*/
182/* Private function prototypes -----------------------------------------------*/
183/* Exported functions --------------------------------------------------------*/
184
188
189#if defined(FMC_Bank1)
190
214
231
239HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
240 const FMC_NORSRAM_InitTypeDef *Init)
241{
242 uint32_t flashaccess;
243 uint32_t btcr_reg;
244 uint32_t mask;
245
246 /* Check the parameters */
247 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
248 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank));
249 assert_param(IS_FMC_MUX(Init->DataAddressMux));
250 assert_param(IS_FMC_MEMORY(Init->MemoryType));
251 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
252 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode));
253 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity));
254#if defined(FMC_BCR1_WRAPMOD)
255 assert_param(IS_FMC_WRAP_MODE(Init->WrapMode));
256#endif /* FMC_BCR1_WRAPMOD */
257 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
258 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation));
259 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal));
260 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode));
261 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait));
262 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst));
263#if defined(FMC_BCR1_CCLKEN)
264 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock));
265#endif /* FMC_BCR1_CCLKEN */
266#if defined(FMC_BCR1_WFDIS)
267 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo));
268#endif /* FMC_BCR1_WFDIS */
269 assert_param(IS_FMC_PAGESIZE(Init->PageSize));
270
271 /* Disable NORSRAM Device */
272 __FMC_NORSRAM_DISABLE(Device, Init->NSBank);
273
274 /* Set NORSRAM device control parameters */
275 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR)
276 {
277 flashaccess = FMC_NORSRAM_FLASH_ACCESS_ENABLE;
278 }
279 else
280 {
281 flashaccess = FMC_NORSRAM_FLASH_ACCESS_DISABLE;
282 }
283
284 btcr_reg = (flashaccess | \
285 Init->DataAddressMux | \
286 Init->MemoryType | \
287 Init->MemoryDataWidth | \
288 Init->BurstAccessMode | \
289 Init->WaitSignalPolarity | \
290 Init->WaitSignalActive | \
291 Init->WriteOperation | \
292 Init->WaitSignal | \
293 Init->ExtendedMode | \
294 Init->AsynchronousWait | \
295 Init->WriteBurst);
296
297#if defined(FMC_BCR1_WRAPMOD)
298 btcr_reg |= Init->WrapMode;
299#endif /* FMC_BCR1_WRAPMOD */
300#if defined(FMC_BCR1_CCLKEN)
301 btcr_reg |= Init->ContinuousClock;
302#endif /* FMC_BCR1_CCLKEN */
303#if defined(FMC_BCR1_WFDIS)
304 btcr_reg |= Init->WriteFifo;
305#endif /* FMC_BCR1_WFDIS */
306 btcr_reg |= Init->PageSize;
307
308 mask = (FMC_BCR1_MBKEN |
309 FMC_BCR1_MUXEN |
310 FMC_BCR1_MTYP |
311 FMC_BCR1_MWID |
312 FMC_BCR1_FACCEN |
313 FMC_BCR1_BURSTEN |
314 FMC_BCR1_WAITPOL |
315 FMC_BCR1_WAITCFG |
316 FMC_BCR1_WREN |
317 FMC_BCR1_WAITEN |
318 FMC_BCR1_EXTMOD |
319 FMC_BCR1_ASYNCWAIT |
320 FMC_BCR1_CBURSTRW);
321
322#if defined(FMC_BCR1_WRAPMOD)
323 mask |= FMC_BCR1_WRAPMOD;
324#endif /* FMC_BCR1_WRAPMOD */
325#if defined(FMC_BCR1_CCLKEN)
326 mask |= FMC_BCR1_CCLKEN;
327#endif /* FMC_BCR1_CCLKEN */
328#if defined(FMC_BCR1_WFDIS)
329 mask |= FMC_BCR1_WFDIS;
330#endif /* FMC_BCR1_WFDIS */
331 mask |= FMC_BCR1_CPSIZE;
332
333 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
334
335#if defined(FMC_BCR1_CCLKEN)
336 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
337 if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BANK1))
338 {
339 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);
340 }
341#endif /* FMC_BCR1_CCLKEN */
342#if defined(FMC_BCR1_WFDIS)
343
344 if (Init->NSBank != FMC_NORSRAM_BANK1)
345 {
346 /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
347 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
348 }
349#endif /* FMC_BCR1_WFDIS */
350
351 return HAL_OK;
352}
353
361HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
362 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
363{
364 /* Check the parameters */
365 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
366 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
367 assert_param(IS_FMC_NORSRAM_BANK(Bank));
368
369 /* Disable the FMC_NORSRAM device */
370 __FMC_NORSRAM_DISABLE(Device, Bank);
371
372 /* De-initialize the FMC_NORSRAM device */
373 /* FMC_NORSRAM_BANK1 */
374 if (Bank == FMC_NORSRAM_BANK1)
375 {
376 Device->BTCR[Bank] = 0x000030DBU;
377 }
378 /* FMC_NORSRAM_BANK2, FMC_NORSRAM_BANK3 or FMC_NORSRAM_BANK4 */
379 else
380 {
381 Device->BTCR[Bank] = 0x000030D2U;
382 }
383
384 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
385 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
386
387 return HAL_OK;
388}
389
398HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
399 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
400{
401#if defined(FMC_BCR1_CCLKEN)
402 uint32_t tmpr;
403#endif /* FMC_BCR1_CCLKEN */
404
405 /* Check the parameters */
406 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
407 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
408 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
409 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
410 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
411 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision));
412 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency));
413 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
414 assert_param(IS_FMC_NORSRAM_BANK(Bank));
415
416 /* Set FMC_NORSRAM device timing parameters */
417 Device->BTCR[Bank + 1U] =
418 (Timing->AddressSetupTime << FMC_BTR1_ADDSET_Pos) |
419 (Timing->AddressHoldTime << FMC_BTR1_ADDHLD_Pos) |
420 (Timing->DataSetupTime << FMC_BTR1_DATAST_Pos) |
421 (Timing->BusTurnAroundDuration << FMC_BTR1_BUSTURN_Pos) |
422 ((Timing->CLKDivision - 1U) << FMC_BTR1_CLKDIV_Pos) |
423 ((Timing->DataLatency - 2U) << FMC_BTR1_DATLAT_Pos) |
424 Timing->AccessMode;
425
426#if defined(FMC_BCR1_CCLKEN)
427 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
428 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))
429 {
430 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos));
431 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos);
432 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr);
433 }
434
435#endif /* FMC_BCR1_CCLKEN */
436 return HAL_OK;
437}
438
451HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
452 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
453 uint32_t ExtendedMode)
454{
455 /* Check the parameters */
456 assert_param(IS_FMC_EXTENDED_MODE(ExtendedMode));
457
458 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
459 if (ExtendedMode == FMC_EXTENDED_MODE_ENABLE)
460 {
461 /* Check the parameters */
462 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));
463 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
464 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
465 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime));
466 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
467 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode));
468 assert_param(IS_FMC_NORSRAM_BANK(Bank));
469
470 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
471 MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
472 ((Timing->AddressHoldTime) << FMC_BWTR1_ADDHLD_Pos) |
473 ((Timing->DataSetupTime) << FMC_BWTR1_DATAST_Pos) |
474 Timing->AccessMode |
475 ((Timing->BusTurnAroundDuration) << FMC_BWTR1_BUSTURN_Pos)));
476 }
477 else
478 {
479 Device->BWTR[Bank] = 0x0FFFFFFFU;
480 }
481
482 return HAL_OK;
483}
487
502
509HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
510{
511 /* Check the parameters */
512 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
513 assert_param(IS_FMC_NORSRAM_BANK(Bank));
514
515 /* Enable write operation */
516 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
517
518 return HAL_OK;
519}
520
527HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
528{
529 /* Check the parameters */
530 assert_param(IS_FMC_NORSRAM_DEVICE(Device));
531 assert_param(IS_FMC_NORSRAM_BANK(Bank));
532
533 /* Disable write operation */
534 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);
535
536 return HAL_OK;
537}
538
542
546#endif /* FMC_Bank1 */
547
548#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
549
574
591
599HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init)
600{
601 /* Check the parameters */
602 assert_param(IS_FMC_NAND_DEVICE(Device));
603 assert_param(IS_FMC_NAND_BANK(Init->NandBank));
604 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
605 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
606 assert_param(IS_FMC_ECC_STATE(Init->EccComputation));
607 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize));
608 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
609 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
610
611#if defined(FMC_Bank2_3)
612 /* Set NAND device control parameters */
613 if (Init->NandBank == FMC_NAND_BANK2)
614 {
615 /* NAND bank 2 registers configuration */
616 MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |
617 FMC_PCR_MEMORY_TYPE_NAND |
618 Init->MemoryDataWidth |
619 Init->EccComputation |
620 Init->ECCPageSize |
621 ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) |
622 ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos)));
623 }
624 else
625 {
626 /* NAND bank 3 registers configuration */
627 MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |
628 FMC_PCR_MEMORY_TYPE_NAND |
629 Init->MemoryDataWidth |
630 Init->EccComputation |
631 Init->ECCPageSize |
632 ((Init->TCLRSetupTime) << FMC_PCR2_TCLR_Pos) |
633 ((Init->TARSetupTime) << FMC_PCR2_TAR_Pos)));
634 }
635#else
636 /* NAND bank 3 registers configuration */
637 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature |
638 FMC_PCR_MEMORY_TYPE_NAND |
639 Init->MemoryDataWidth |
640 Init->EccComputation |
641 Init->ECCPageSize |
642 ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) |
643 ((Init->TARSetupTime) << FMC_PCR_TAR_Pos)));
644#endif /* FMC_Bank2_3 */
645
646 return HAL_OK;
647}
648
657HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
658 const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
659{
660 /* Check the parameters */
661 assert_param(IS_FMC_NAND_DEVICE(Device));
662 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
663 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
664 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
665 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
666 assert_param(IS_FMC_NAND_BANK(Bank));
667
668#if defined(FMC_Bank2_3)
669 /* Set FMC_NAND device timing parameters */
670 if (Bank == FMC_NAND_BANK2)
671 {
672 /* NAND bank 2 registers configuration */
673 WRITE_REG(Device->PMEM2, (Timing->SetupTime |
674 ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) |
675 ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) |
676 ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos)));
677 }
678 else
679 {
680 /* NAND bank 3 registers configuration */
681 WRITE_REG(Device->PMEM3, (Timing->SetupTime |
682 ((Timing->WaitSetupTime) << FMC_PMEM2_MEMWAIT2_Pos) |
683 ((Timing->HoldSetupTime) << FMC_PMEM2_MEMHOLD2_Pos) |
684 ((Timing->HiZSetupTime) << FMC_PMEM2_MEMHIZ2_Pos)));
685 }
686#else
687 /* Prevent unused argument(s) compilation warning if no assert_param check */
688 UNUSED(Bank);
689
690 /* NAND bank 3 registers configuration */
691 Device->PMEM = (Timing->SetupTime |
692 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT2_Pos) |
693 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD2_Pos) |
694 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ2_Pos));
695#endif /* FMC_Bank2_3 */
696
697 return HAL_OK;
698}
699
708HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
709 const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
710{
711 /* Check the parameters */
712 assert_param(IS_FMC_NAND_DEVICE(Device));
713 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
714 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
715 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
716 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
717 assert_param(IS_FMC_NAND_BANK(Bank));
718
719#if defined(FMC_Bank2_3)
720 /* Set FMC_NAND device timing parameters */
721 if (Bank == FMC_NAND_BANK2)
722 {
723 /* NAND bank 2 registers configuration */
724 WRITE_REG(Device->PATT2, (Timing->SetupTime |
725 ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) |
726 ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) |
727 ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos)));
728 }
729 else
730 {
731 /* NAND bank 3 registers configuration */
732 WRITE_REG(Device->PATT3, (Timing->SetupTime |
733 ((Timing->WaitSetupTime) << FMC_PATT2_ATTWAIT2_Pos) |
734 ((Timing->HoldSetupTime) << FMC_PATT2_ATTHOLD2_Pos) |
735 ((Timing->HiZSetupTime) << FMC_PATT2_ATTHIZ2_Pos)));
736 }
737#else
738 /* Prevent unused argument(s) compilation warning if no assert_param check */
739 UNUSED(Bank);
740
741 /* NAND bank 3 registers configuration */
742 Device->PATT = (Timing->SetupTime |
743 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT2_Pos) |
744 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD2_Pos) |
745 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ2_Pos));
746#endif /* FMC_Bank2_3 */
747
748 return HAL_OK;
749}
750
757HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
758{
759 /* Check the parameters */
760 assert_param(IS_FMC_NAND_DEVICE(Device));
761 assert_param(IS_FMC_NAND_BANK(Bank));
762
763 /* Disable the NAND Bank */
764 __FMC_NAND_DISABLE(Device, Bank);
765
766 /* De-initialize the NAND Bank */
767#if defined(FMC_Bank2_3)
768 if (Bank == FMC_NAND_BANK2)
769 {
770 /* Set the FMC_NAND_BANK2 registers to their reset values */
771 WRITE_REG(Device->PCR2, 0x00000018U);
772 WRITE_REG(Device->SR2, 0x00000040U);
773 WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
774 WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
775 }
776 /* FMC_Bank3_NAND */
777 else
778 {
779 /* Set the FMC_NAND_BANK3 registers to their reset values */
780 WRITE_REG(Device->PCR3, 0x00000018U);
781 WRITE_REG(Device->SR3, 0x00000040U);
782 WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
783 WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
784 }
785#else
786 /* Prevent unused argument(s) compilation warning if no assert_param check */
787 UNUSED(Bank);
788
789 /* Set the FMC_NAND_BANK3 registers to their reset values */
790 WRITE_REG(Device->PCR, 0x00000018U);
791 WRITE_REG(Device->SR, 0x00000040U);
792 WRITE_REG(Device->PMEM, 0xFCFCFCFCU);
793 WRITE_REG(Device->PATT, 0xFCFCFCFCU);
794#endif /* FMC_Bank2_3 */
795
796 return HAL_OK;
797}
798
802
817
818
825HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
826{
827 /* Check the parameters */
828 assert_param(IS_FMC_NAND_DEVICE(Device));
829 assert_param(IS_FMC_NAND_BANK(Bank));
830
831 /* Enable ECC feature */
832#if defined(FMC_Bank2_3)
833 if (Bank == FMC_NAND_BANK2)
834 {
835 SET_BIT(Device->PCR2, FMC_PCR2_ECCEN);
836 }
837 else
838 {
839 SET_BIT(Device->PCR3, FMC_PCR2_ECCEN);
840 }
841#else
842 /* Prevent unused argument(s) compilation warning if no assert_param check */
843 UNUSED(Bank);
844
845 SET_BIT(Device->PCR, FMC_PCR_ECCEN);
846#endif /* FMC_Bank2_3 */
847
848 return HAL_OK;
849}
850
851
858HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
859{
860 /* Check the parameters */
861 assert_param(IS_FMC_NAND_DEVICE(Device));
862 assert_param(IS_FMC_NAND_BANK(Bank));
863
864 /* Disable ECC feature */
865#if defined(FMC_Bank2_3)
866 if (Bank == FMC_NAND_BANK2)
867 {
868 CLEAR_BIT(Device->PCR2, FMC_PCR2_ECCEN);
869 }
870 else
871 {
872 CLEAR_BIT(Device->PCR3, FMC_PCR2_ECCEN);
873 }
874#else
875 /* Prevent unused argument(s) compilation warning if no assert_param check */
876 UNUSED(Bank);
877
878 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);
879#endif /* FMC_Bank2_3 */
880
881 return HAL_OK;
882}
883
892HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
893 uint32_t Timeout)
894{
895 uint32_t tickstart;
896
897 /* Check the parameters */
898 assert_param(IS_FMC_NAND_DEVICE(Device));
899 assert_param(IS_FMC_NAND_BANK(Bank));
900
901 /* Get tick */
902 tickstart = HAL_GetTick();
903
904 /* Wait until FIFO is empty */
905 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)
906 {
907 /* Check for the Timeout */
908 if (Timeout != HAL_MAX_DELAY)
909 {
910 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
911 {
912 return HAL_TIMEOUT;
913 }
914 }
915 }
916
917#if defined(FMC_Bank2_3)
918 if (Bank == FMC_NAND_BANK2)
919 {
920 /* Get the ECCR2 register value */
921 *ECCval = (uint32_t)Device->ECCR2;
922 }
923 else
924 {
925 /* Get the ECCR3 register value */
926 *ECCval = (uint32_t)Device->ECCR3;
927 }
928#else
929 /* Prevent unused argument(s) compilation warning if no assert_param check */
930 UNUSED(Bank);
931
932 /* Get the ECCR register value */
933 *ECCval = (uint32_t)Device->ECCR;
934#endif /* FMC_Bank2_3 */
935
936 return HAL_OK;
937}
938
942#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
943
944#if defined(FMC_Bank4)
945
968
985
993HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, const FMC_PCCARD_InitTypeDef *Init)
994{
995 /* Check the parameters */
996 assert_param(IS_FMC_PCCARD_DEVICE(Device));
997#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
998 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature));
999 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime));
1000 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime));
1001#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
1002
1003 /* Set FMC_PCCARD device control parameters */
1004 MODIFY_REG(Device->PCR4,
1005 (FMC_PCR4_PTYP |
1006 FMC_PCR4_PWAITEN |
1007 FMC_PCR4_PWID |
1008 FMC_PCR4_TCLR |
1009 FMC_PCR4_TAR),
1010 (FMC_PCR_MEMORY_TYPE_PCCARD |
1011 Init->Waitfeature |
1012 FMC_NAND_PCC_MEM_BUS_WIDTH_16 |
1013 (Init->TCLRSetupTime << FMC_PCR4_TCLR_Pos) |
1014 (Init->TARSetupTime << FMC_PCR4_TAR_Pos)));
1015
1016 return HAL_OK;
1017}
1018
1026HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
1027 const FMC_NAND_PCC_TimingTypeDef *Timing)
1028{
1029 /* Check the parameters */
1030 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1031#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
1032 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1033 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1034 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1035 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1036#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
1037
1038 /* Set PCCARD timing parameters */
1039 WRITE_REG(Device->PMEM4, (Timing->SetupTime |
1040 ((Timing->WaitSetupTime) << FMC_PMEM4_MEMWAIT4_Pos) |
1041 ((Timing->HoldSetupTime) << FMC_PMEM4_MEMHOLD4_Pos) |
1042 ((Timing->HiZSetupTime) << FMC_PMEM4_MEMHIZ4_Pos)));
1043
1044 return HAL_OK;
1045}
1046
1054HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
1055 const FMC_NAND_PCC_TimingTypeDef *Timing)
1056{
1057 /* Check the parameters */
1058 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1059#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
1060 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1061 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1062 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1063 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1064#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
1065
1066 /* Set PCCARD timing parameters */
1067 WRITE_REG(Device->PATT4, (Timing->SetupTime |
1068 ((Timing->WaitSetupTime) << FMC_PATT4_ATTWAIT4_Pos) |
1069 ((Timing->HoldSetupTime) << FMC_PATT4_ATTHOLD4_Pos) |
1070 ((Timing->HiZSetupTime) << FMC_PATT4_ATTHIZ4_Pos)));
1071
1072 return HAL_OK;
1073}
1074
1082HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
1083 const FMC_NAND_PCC_TimingTypeDef *Timing)
1084{
1085 /* Check the parameters */
1086 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1087#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
1088 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime));
1089 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime));
1090 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime));
1091 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime));
1092#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
1093
1094 /* Set FMC_PCCARD device timing parameters */
1095 WRITE_REG(Device->PIO4, (Timing->SetupTime |
1096 (Timing->WaitSetupTime << FMC_PIO4_IOWAIT4_Pos) |
1097 (Timing->HoldSetupTime << FMC_PIO4_IOHOLD4_Pos) |
1098 (Timing->HiZSetupTime << FMC_PIO4_IOHIZ4_Pos)));
1099
1100 return HAL_OK;
1101}
1102
1108HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
1109{
1110 /* Check the parameters */
1111 assert_param(IS_FMC_PCCARD_DEVICE(Device));
1112
1113 /* Disable the FMC_PCCARD device */
1114 __FMC_PCCARD_DISABLE(Device);
1115
1116 /* De-initialize the FMC_PCCARD device */
1117 Device->PCR4 = 0x00000018U;
1118 Device->SR4 = 0x00000040U;
1119 Device->PMEM4 = 0xFCFCFCFCU;
1120 Device->PATT4 = 0xFCFCFCFCU;
1121 Device->PIO4 = 0xFCFCFCFCU;
1122
1123 return HAL_OK;
1124}
1125
1129#endif /* FMC_Bank4 */
1130
1131#if defined(FMC_Bank5_6)
1132
1154
1171
1179HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init)
1180{
1181 /* Check the parameters */
1182 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1183 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank));
1184 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber));
1185 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber));
1186 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth));
1187 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber));
1188 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency));
1189 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection));
1190 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod));
1191 assert_param(IS_FMC_READ_BURST(Init->ReadBurst));
1192 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay));
1193
1194 /* Set SDRAM bank configuration parameters */
1195 if (Init->SDBank == FMC_SDRAM_BANK1)
1196 {
1197 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
1198 SDCR_CLEAR_MASK,
1199 (Init->ColumnBitsNumber |
1200 Init->RowBitsNumber |
1201 Init->MemoryDataWidth |
1202 Init->InternalBankNumber |
1203 Init->CASLatency |
1204 Init->WriteProtection |
1205 Init->SDClockPeriod |
1206 Init->ReadBurst |
1207 Init->ReadPipeDelay));
1208 }
1209 else /* FMC_Bank2_SDRAM */
1210 {
1211 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],
1212 FMC_SDCR1_SDCLK |
1213 FMC_SDCR1_RBURST |
1214 FMC_SDCR1_RPIPE,
1215 (Init->SDClockPeriod |
1216 Init->ReadBurst |
1217 Init->ReadPipeDelay));
1218
1219 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],
1220 SDCR_CLEAR_MASK,
1221 (Init->ColumnBitsNumber |
1222 Init->RowBitsNumber |
1223 Init->MemoryDataWidth |
1224 Init->InternalBankNumber |
1225 Init->CASLatency |
1226 Init->WriteProtection));
1227 }
1228
1229 return HAL_OK;
1230}
1231
1232
1241HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
1242 const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
1243{
1244 /* Check the parameters */
1245 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1246 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay));
1247 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay));
1248 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime));
1249 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay));
1250 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime));
1251 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay));
1252 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay));
1253 assert_param(IS_FMC_SDRAM_BANK(Bank));
1254
1255 /* Set SDRAM device timing parameters */
1256 if (Bank == FMC_SDRAM_BANK1)
1257 {
1258 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
1259 SDTR_CLEAR_MASK,
1260 (((Timing->LoadToActiveDelay) - 1U) |
1261 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) |
1262 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) |
1263 (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) |
1264 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) |
1265 (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) |
1266 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
1267 }
1268 else /* FMC_Bank2_SDRAM */
1269 {
1270 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],
1271 FMC_SDTR1_TRC |
1272 FMC_SDTR1_TRP,
1273 (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) |
1274 (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos));
1275
1276 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],
1277 SDTR_CLEAR_MASK,
1278 (((Timing->LoadToActiveDelay) - 1U) |
1279 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) |
1280 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) |
1281 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) |
1282 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos)));
1283 }
1284
1285 return HAL_OK;
1286}
1287
1293HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1294{
1295 /* Check the parameters */
1296 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1297 assert_param(IS_FMC_SDRAM_BANK(Bank));
1298
1299 /* De-initialize the SDRAM device */
1300 Device->SDCR[Bank] = 0x000002D0U;
1301 Device->SDTR[Bank] = 0x0FFFFFFFU;
1302 Device->SDCMR = 0x00000000U;
1303 Device->SDRTR = 0x00000000U;
1304 Device->SDSR = 0x00000000U;
1305
1306 return HAL_OK;
1307}
1308
1312
1327
1334HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1335{
1336 /* Check the parameters */
1337 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1338 assert_param(IS_FMC_SDRAM_BANK(Bank));
1339
1340 /* Enable write protection */
1341 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
1342
1343 return HAL_OK;
1344}
1345
1351HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1352{
1353 /* Check the parameters */
1354 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1355 assert_param(IS_FMC_SDRAM_BANK(Bank));
1356
1357 /* Disable write protection */
1358 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);
1359
1360 return HAL_OK;
1361}
1362
1371HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
1372 const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
1373{
1374 uint32_t tickstart = 0U;
1375 /* Check the parameters */
1376 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1377 assert_param(IS_FMC_COMMAND_MODE(Command->CommandMode));
1378 assert_param(IS_FMC_COMMAND_TARGET(Command->CommandTarget));
1379 assert_param(IS_FMC_AUTOREFRESH_NUMBER(Command->AutoRefreshNumber));
1380 assert_param(IS_FMC_MODE_REGISTER(Command->ModeRegisterDefinition));
1381
1382 /* Set command register */
1383 MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC_SDCMR_MRD),
1384 ((Command->CommandMode) | (Command->CommandTarget) |
1385 (((Command->AutoRefreshNumber) - 1U) << FMC_SDCMR_NRFS_Pos) |
1386 ((Command->ModeRegisterDefinition) << FMC_SDCMR_MRD_Pos)));
1387 /* Get tick */
1388 tickstart = HAL_GetTick();
1389
1390 /* wait until command is send */
1391 while (HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
1392 {
1393 /* Check for the Timeout */
1394 if (Timeout != HAL_MAX_DELAY)
1395 {
1396 if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
1397 {
1398 return HAL_TIMEOUT;
1399 }
1400 }
1401 }
1402 return HAL_OK;
1403}
1404
1411HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
1412{
1413 /* Check the parameters */
1414 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1415 assert_param(IS_FMC_REFRESH_RATE(RefreshRate));
1416
1417 /* Set the refresh rate in command register */
1418 MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos));
1419
1420 return HAL_OK;
1421}
1422
1429HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
1430 uint32_t AutoRefreshNumber)
1431{
1432 /* Check the parameters */
1433 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1434 assert_param(IS_FMC_AUTOREFRESH_NUMBER(AutoRefreshNumber));
1435
1436 /* Set the Auto-refresh number in command register */
1437 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));
1438
1439 return HAL_OK;
1440}
1441
1451uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)
1452{
1453 uint32_t tmpreg;
1454
1455 /* Check the parameters */
1456 assert_param(IS_FMC_SDRAM_DEVICE(Device));
1457 assert_param(IS_FMC_SDRAM_BANK(Bank));
1458
1459 /* Get the corresponding bank mode */
1460 if (Bank == FMC_SDRAM_BANK1)
1461 {
1462 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);
1463 }
1464 else
1465 {
1466 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);
1467 }
1468
1469 /* Return the mode status */
1470 return tmpreg;
1471}
1472
1476
1480
1481#endif /* FMC_Bank5_6 */
1482
1486
1490
1491#endif /* HAL_NOR_MODULE_ENABLED */
FMC_NAND_TypeDef
#define FMC_NAND_TypeDef
Definition stm32f4xx_ll_fmc.h:203
FMC_NORSRAM_TimingTypeDef
#define FMC_NORSRAM_TimingTypeDef
Definition stm32f4xx_ll_fsmc.h:669
FMC_NORSRAM_DeInit
#define FMC_NORSRAM_DeInit
Definition stm32f4xx_ll_fsmc.h:674
FMC_NORSRAM_TypeDef
#define FMC_NORSRAM_TypeDef
Definition stm32f4xx_ll_fsmc.h:666
FMC_NORSRAM_Timing_Init
#define FMC_NORSRAM_Timing_Init
Definition stm32f4xx_ll_fsmc.h:672
FMC_NORSRAM_EXTENDED_TypeDef
#define FMC_NORSRAM_EXTENDED_TypeDef
Definition stm32f4xx_ll_fsmc.h:667
FMC_NORSRAM_WriteOperation_Disable
#define FMC_NORSRAM_WriteOperation_Disable
Definition stm32f4xx_ll_fsmc.h:676
FMC_NORSRAM_WriteOperation_Enable
#define FMC_NORSRAM_WriteOperation_Enable
Definition stm32f4xx_ll_fsmc.h:675
FMC_WRITE_OPERATION_ENABLE
#define FMC_WRITE_OPERATION_ENABLE
Definition stm32f4xx_ll_fsmc.h:660
__FMC_NORSRAM_DISABLE
#define __FMC_NORSRAM_DISABLE
Definition stm32f4xx_ll_fsmc.h:679
FMC_NORSRAM_Extended_Timing_Init
#define FMC_NORSRAM_Extended_Timing_Init
Definition stm32f4xx_ll_fsmc.h:673
FMC_NORSRAM_InitTypeDef
#define FMC_NORSRAM_InitTypeDef
Definition stm32f4xx_ll_fsmc.h:668
FMC_NORSRAM_Init
#define FMC_NORSRAM_Init
Definition stm32f4xx_ll_fsmc.h:671
FMC_NORSRAM_BANK1
#define FMC_NORSRAM_BANK1
Definition stm32f4xx_ll_fsmc.h:729
FMC_FLAG_FEMPT
#define FMC_FLAG_FEMPT
Definition stm32f4xx_ll_fsmc.h:741
HAL_GetTick
uint32_t HAL_GetTick(void)
Provides a tick value in millisecond.
Definition stm32f4xx_hal.c:323
assert_param
#define assert_param(expr)
Definition stm32_assert_template.h:46
stm32f4xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
HAL_IS_BIT_SET
#define HAL_IS_BIT_SET(REG, BIT)
Definition stm32f4xx_hal_def.h:63
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition stm32f4xx_hal_def.h:39
HAL_TIMEOUT
@ HAL_TIMEOUT
Definition stm32f4xx_hal_def.h:43
HAL_OK
@ HAL_OK
Definition stm32f4xx_hal_def.h:40
HAL_MAX_DELAY
#define HAL_MAX_DELAY
Definition stm32f4xx_hal_def.h:61