STM32F4xx HAL Driver master
STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_ll_fmc.h
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1
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32F4xx_LL_FMC_H
21#define STM32F4xx_LL_FMC_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f4xx_hal_def.h"
29
33
37
41#if defined(FMC_Bank1)
42
43#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \
44 ((__BANK__) == FMC_NORSRAM_BANK2) || \
45 ((__BANK__) == FMC_NORSRAM_BANK3) || \
46 ((__BANK__) == FMC_NORSRAM_BANK4))
47#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
48 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
49#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
50 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
51 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
52#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
53 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
54 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
55#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
56 ((__SIZE__) == FMC_PAGE_SIZE_128) || \
57 ((__SIZE__) == FMC_PAGE_SIZE_256) || \
58 ((__SIZE__) == FMC_PAGE_SIZE_512) || \
59 ((__SIZE__) == FMC_PAGE_SIZE_1024))
60#if defined(FMC_BCR1_WFDIS)
61#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
62 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
63#endif /* FMC_BCR1_WFDIS */
64#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
65 ((__MODE__) == FMC_ACCESS_MODE_B) || \
66 ((__MODE__) == FMC_ACCESS_MODE_C) || \
67 ((__MODE__) == FMC_ACCESS_MODE_D))
68#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
69 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
70#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
71 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
72#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) || \
73 ((__MODE__) == FMC_WRAP_MODE_ENABLE))
74#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
75 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
76#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
77 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
78#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
79 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
80#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
81 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
82#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
83 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
84#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
85#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
86 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
87#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
88 ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
89#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
90#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
91#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
92#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
93#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
94#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
95#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
96#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
97
98#endif /* FMC_Bank1 */
99#if (defined(FMC_Bank3) || defined(FMC_Bank2_3))
100
101#if defined(FMC_Bank2_3)
102#define IS_FMC_NAND_BANK(__BANK__) (((__BANK__) == FMC_NAND_BANK2) || \
103 ((__BANK__) == FMC_NAND_BANK3))
104#else
105#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)
106#endif /* FMC_Bank2_3 */
107#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
108 ((__FEATURE__) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
109#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
110 ((__WIDTH__) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
111#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \
112 ((__STATE__) == FMC_NAND_ECC_ENABLE))
113
114#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
115 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
116 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
117 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
118 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
119 ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
120#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
121#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
122#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
123#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
124#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
125#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
126#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
127
128#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
129#if defined(FMC_Bank4)
130#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
131
132#endif /* FMC_Bank4 */
133#if defined(FMC_Bank5_6)
134
135#define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
136 ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
137 ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32))
138#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
139 ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
140#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \
141 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \
142 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
143#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \
144 ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
145#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \
146 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \
147 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
148#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \
149 ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \
150 ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \
151 ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
152 ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \
153 ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
154 ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
155#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \
156 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \
157 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
158#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
159#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
160#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))
161#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
162#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))
163#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
164#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))
165#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U))
166#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U)
167#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U)
168#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
169#define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \
170 ((__BANK__) == FMC_SDRAM_BANK2))
171#define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
172 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
173 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
174 ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11))
175#define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \
176 ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \
177 ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13))
178#define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
179 ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4))
180#define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \
181 ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \
182 ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3))
183
184#endif /* FMC_Bank5_6 */
185
189
190/* Exported typedef ----------------------------------------------------------*/
191
195
196#if defined(FMC_Bank1)
197#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
198#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
199#endif /* FMC_Bank1 */
200#if defined(FMC_Bank2_3)
201#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
202#else
203#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
204#endif /* FMC_Bank2_3 */
205#if defined(FMC_Bank4)
206#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
207#endif /* FMC_Bank4 */
208#if defined(FMC_Bank5_6)
209#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
210#endif /* FMC_Bank5_6 */
211
212#if defined(FMC_Bank1)
213#define FMC_NORSRAM_DEVICE FMC_Bank1
214#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
215#endif /* FMC_Bank1 */
216#if defined(FMC_Bank2_3)
217#define FMC_NAND_DEVICE FMC_Bank2_3
218#else
219#define FMC_NAND_DEVICE FMC_Bank3
220#endif /* FMC_Bank2_3 */
221#if defined(FMC_Bank4)
222#define FMC_PCCARD_DEVICE FMC_Bank4
223#endif /* FMC_Bank4 */
224#if defined(FMC_Bank5_6)
225#define FMC_SDRAM_DEVICE FMC_Bank5_6
226#endif /* FMC_Bank5_6 */
227
228#if defined(FMC_Bank1)
232typedef struct
233{
234 uint32_t NSBank;
236
237 uint32_t DataAddressMux;
240
241 uint32_t MemoryType;
244
245 uint32_t MemoryDataWidth;
247
248 uint32_t BurstAccessMode;
251
252 uint32_t WaitSignalPolarity;
255
256 uint32_t WrapMode;
260
261 uint32_t WaitSignalActive;
265
266 uint32_t WriteOperation;
269
270 uint32_t WaitSignal;
273
274 uint32_t ExtendedMode;
276
277 uint32_t AsynchronousWait;
280
281 uint32_t WriteBurst;
283
284 uint32_t ContinuousClock;
288
289 uint32_t WriteFifo;
294
295 uint32_t PageSize;
297} FMC_NORSRAM_InitTypeDef;
298
302typedef struct
303{
304 uint32_t AddressSetupTime;
308
309 uint32_t AddressHoldTime;
313
314 uint32_t DataSetupTime;
319
320 uint32_t BusTurnAroundDuration;
324
325 uint32_t CLKDivision;
330
331 uint32_t DataLatency;
338
339 uint32_t AccessMode;
341} FMC_NORSRAM_TimingTypeDef;
342#endif /* FMC_Bank1 */
343
344#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
348typedef struct
349{
350 uint32_t NandBank;
352
353 uint32_t Waitfeature;
355
356 uint32_t MemoryDataWidth;
358
359 uint32_t EccComputation;
361
362 uint32_t ECCPageSize;
364
365 uint32_t TCLRSetupTime;
368
369 uint32_t TARSetupTime;
372} FMC_NAND_InitTypeDef;
373#endif /* FMC_Bank3 || FMC_Bank2_3 */
374
375#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4)
379typedef struct
380{
381 uint32_t SetupTime;
386
387 uint32_t WaitSetupTime;
392
393 uint32_t HoldSetupTime;
399
400 uint32_t HiZSetupTime;
405} FMC_NAND_PCC_TimingTypeDef;
406#endif /* FMC_Bank3 || FMC_Bank2_3 */
407
408#if defined(FMC_Bank4)
412typedef struct
413{
414 uint32_t Waitfeature;
416
417 uint32_t TCLRSetupTime;
420
421 uint32_t TARSetupTime;
424} FMC_PCCARD_InitTypeDef;
425#endif /* FMC_Bank4 */
426
427#if defined(FMC_Bank5_6)
431typedef struct
432{
433 uint32_t SDBank;
435
436 uint32_t ColumnBitsNumber;
438
439 uint32_t RowBitsNumber;
441
442 uint32_t MemoryDataWidth;
444
445 uint32_t InternalBankNumber;
447
448 uint32_t CASLatency;
450
451 uint32_t WriteProtection;
453
454 uint32_t SDClockPeriod;
457
458 uint32_t ReadBurst;
461
462 uint32_t ReadPipeDelay;
464} FMC_SDRAM_InitTypeDef;
465
469typedef struct
470{
471 uint32_t LoadToActiveDelay;
474
475 uint32_t ExitSelfRefreshDelay;
478
479 uint32_t SelfRefreshTime;
482
483 uint32_t RowCycleDelay;
487
488 uint32_t WriteRecoveryTime;
490
491 uint32_t RPDelay;
494
495 uint32_t RCDDelay;
498} FMC_SDRAM_TimingTypeDef;
499
503typedef struct
504{
505 uint32_t CommandMode;
507
508 uint32_t CommandTarget;
510
511 uint32_t AutoRefreshNumber;
514
515 uint32_t ModeRegisterDefinition;
516} FMC_SDRAM_CommandTypeDef;
517#endif /* FMC_Bank5_6 */
521
522/* Exported constants --------------------------------------------------------*/
526#if defined(FMC_Bank1)
527
531
535#define FMC_NORSRAM_BANK1 (0x00000000U)
536#define FMC_NORSRAM_BANK2 (0x00000002U)
537#define FMC_NORSRAM_BANK3 (0x00000004U)
538#define FMC_NORSRAM_BANK4 (0x00000006U)
542
546#define FMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
547#define FMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
551
555#define FMC_MEMORY_TYPE_SRAM (0x00000000U)
556#define FMC_MEMORY_TYPE_PSRAM (0x00000004U)
557#define FMC_MEMORY_TYPE_NOR (0x00000008U)
561
565#define FMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
566#define FMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
567#define FMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
571
575#define FMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
576#define FMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
580
584#define FMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
585#define FMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
589
593#define FMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
594#define FMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
598
603#define FMC_WRAP_MODE_DISABLE (0x00000000U)
604#define FMC_WRAP_MODE_ENABLE (0x00000400U)
608
612#define FMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
613#define FMC_WAIT_TIMING_DURING_WS (0x00000800U)
617
621#define FMC_WRITE_OPERATION_DISABLE (0x00000000U)
622#define FMC_WRITE_OPERATION_ENABLE (0x00001000U)
626
630#define FMC_WAIT_SIGNAL_DISABLE (0x00000000U)
631#define FMC_WAIT_SIGNAL_ENABLE (0x00002000U)
635
639#define FMC_EXTENDED_MODE_DISABLE (0x00000000U)
640#define FMC_EXTENDED_MODE_ENABLE (0x00004000U)
644
648#define FMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
649#define FMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
653
657#define FMC_PAGE_SIZE_NONE (0x00000000U)
658#define FMC_PAGE_SIZE_128 FMC_BCR1_CPSIZE_0
659#define FMC_PAGE_SIZE_256 FMC_BCR1_CPSIZE_1
660#define FMC_PAGE_SIZE_512 (FMC_BCR1_CPSIZE_0\
661 | FMC_BCR1_CPSIZE_1)
662#define FMC_PAGE_SIZE_1024 FMC_BCR1_CPSIZE_2
666
670#define FMC_WRITE_BURST_DISABLE (0x00000000U)
671#define FMC_WRITE_BURST_ENABLE (0x00080000U)
675
679#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
680#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
684
685#if defined(FMC_BCR1_WFDIS)
690#define FMC_WRITE_FIFO_DISABLE FMC_BCR1_WFDIS
691#define FMC_WRITE_FIFO_ENABLE (0x00000000U)
692#endif /* FMC_BCR1_WFDIS */
696
700#define FMC_ACCESS_MODE_A (0x00000000U)
701#define FMC_ACCESS_MODE_B (0x10000000U)
702#define FMC_ACCESS_MODE_C (0x20000000U)
703#define FMC_ACCESS_MODE_D (0x30000000U)
707
711#endif /* FMC_Bank1 */
712
713#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4)
714
721#if defined(FMC_Bank2_3)
722#define FMC_NAND_BANK2 (0x00000010U)
723#endif /* FMC_Bank2_3 */
724#define FMC_NAND_BANK3 (0x00000100U)
728
732#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U)
733#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U)
737
741#if defined(FMC_Bank4)
742#define FMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U)
743#endif /* FMC_Bank4 */
744#define FMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
748
752#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U)
753#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U)
757
761#define FMC_NAND_ECC_DISABLE (0x00000000U)
762#define FMC_NAND_ECC_ENABLE (0x00000040U)
766
770#define FMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
771#define FMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
772#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
773#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
774#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
775#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
779
783#endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */
784
785#if defined(FMC_Bank5_6)
792#define FMC_SDRAM_BANK1 (0x00000000U)
793#define FMC_SDRAM_BANK2 (0x00000001U)
797
801#define FMC_SDRAM_COLUMN_BITS_NUM_8 (0x00000000U)
802#define FMC_SDRAM_COLUMN_BITS_NUM_9 (0x00000001U)
803#define FMC_SDRAM_COLUMN_BITS_NUM_10 (0x00000002U)
804#define FMC_SDRAM_COLUMN_BITS_NUM_11 (0x00000003U)
808
812#define FMC_SDRAM_ROW_BITS_NUM_11 (0x00000000U)
813#define FMC_SDRAM_ROW_BITS_NUM_12 (0x00000004U)
814#define FMC_SDRAM_ROW_BITS_NUM_13 (0x00000008U)
818
822#define FMC_SDRAM_MEM_BUS_WIDTH_8 (0x00000000U)
823#define FMC_SDRAM_MEM_BUS_WIDTH_16 (0x00000010U)
824#define FMC_SDRAM_MEM_BUS_WIDTH_32 (0x00000020U)
828
832#define FMC_SDRAM_INTERN_BANKS_NUM_2 (0x00000000U)
833#define FMC_SDRAM_INTERN_BANKS_NUM_4 (0x00000040U)
837
841#define FMC_SDRAM_CAS_LATENCY_1 (0x00000080U)
842#define FMC_SDRAM_CAS_LATENCY_2 (0x00000100U)
843#define FMC_SDRAM_CAS_LATENCY_3 (0x00000180U)
847
851#define FMC_SDRAM_WRITE_PROTECTION_DISABLE (0x00000000U)
852#define FMC_SDRAM_WRITE_PROTECTION_ENABLE (0x00000200U)
856
860#define FMC_SDRAM_CLOCK_DISABLE (0x00000000U)
861#define FMC_SDRAM_CLOCK_PERIOD_2 (0x00000800U)
862#define FMC_SDRAM_CLOCK_PERIOD_3 (0x00000C00U)
866
870#define FMC_SDRAM_RBURST_DISABLE (0x00000000U)
871#define FMC_SDRAM_RBURST_ENABLE (0x00001000U)
875
879#define FMC_SDRAM_RPIPE_DELAY_0 (0x00000000U)
880#define FMC_SDRAM_RPIPE_DELAY_1 (0x00002000U)
881#define FMC_SDRAM_RPIPE_DELAY_2 (0x00004000U)
885
889#define FMC_SDRAM_CMD_NORMAL_MODE (0x00000000U)
890#define FMC_SDRAM_CMD_CLK_ENABLE (0x00000001U)
891#define FMC_SDRAM_CMD_PALL (0x00000002U)
892#define FMC_SDRAM_CMD_AUTOREFRESH_MODE (0x00000003U)
893#define FMC_SDRAM_CMD_LOAD_MODE (0x00000004U)
894#define FMC_SDRAM_CMD_SELFREFRESH_MODE (0x00000005U)
895#define FMC_SDRAM_CMD_POWERDOWN_MODE (0x00000006U)
899
903#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
904#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
905#define FMC_SDRAM_CMD_TARGET_BANK1_2 (0x00000018U)
909
913#define FMC_SDRAM_NORMAL_MODE (0x00000000U)
914#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
915#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
919
923
924#endif /* FMC_Bank5_6 */
925
929#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4)
930#define FMC_IT_RISING_EDGE (0x00000008U)
931#define FMC_IT_LEVEL (0x00000010U)
932#define FMC_IT_FALLING_EDGE (0x00000020U)
933#endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */
934#if defined(FMC_Bank5_6)
935#define FMC_IT_REFRESH_ERROR (0x00004000U)
936#endif /* FMC_Bank5_6 */
940
944#if defined(FMC_Bank3) || defined(FMC_Bank2_3) || defined(FMC_Bank4)
945#define FMC_FLAG_RISING_EDGE (0x00000001U)
946#define FMC_FLAG_LEVEL (0x00000002U)
947#define FMC_FLAG_FALLING_EDGE (0x00000004U)
948#define FMC_FLAG_FEMPT (0x00000040U)
949#endif /* FMC_Bank3 || FMC_Bank2_3 || FMC_Bank4 */
950#if defined(FMC_Bank5_6)
951#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
952#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
953#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
954#endif /* FMC_Bank5_6 */
958
962
966
967/* Private macro -------------------------------------------------------------*/
971#if defined(FMC_Bank1)
976
983#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
984 |= FMC_BCR1_MBKEN)
985
992#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
993 &= ~FMC_BCR1_MBKEN)
994
998#endif /* FMC_Bank1 */
999
1000#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
1005
1012#if defined(FMC_Bank2_3)
1013#if defined (FMC_PCR_PBKEN)
1014#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
1015#else
1016#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2) ? \
1017 ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN) : \
1018 ((__INSTANCE__)->PCR3 |= FMC_PCR3_PBKEN))
1019#endif /* FMC_PCR_PBKEN */
1020#else
1021#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
1022#endif /* FMC_Bank2_3 */
1023
1030#if defined(FMC_Bank2_3)
1031#if defined (FMC_PCR_PBKEN)
1032#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
1033#else
1034#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2) ? \
1035 CLEAR_BIT((__INSTANCE__)->PCR2, FMC_PCR2_PBKEN) : \
1036 CLEAR_BIT((__INSTANCE__)->PCR3, FMC_PCR3_PBKEN))
1037#endif /* FMC_PCR_PBKEN */
1038#else
1039#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)
1040#endif /* FMC_Bank2_3 */
1041
1045#endif /* FMC_Bank3 || FMC_Bank2_3 */
1046
1047#if defined(FMC_Bank4)
1057#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
1058
1064#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
1068
1069#endif /* FMC_Bank4 */
1070#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
1075
1087#if defined(FMC_Bank2_3)
1088#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2) ? \
1089 ((__INSTANCE__)->SR2 |= (__INTERRUPT__)) : \
1090 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
1091#else
1092#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
1093#endif /* FMC_Bank2_3 */
1094
1106#if defined(FMC_Bank2_3)
1107#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2) ? \
1108 ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)) : \
1109 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
1110#else
1111#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
1112#endif /* FMC_Bank2_3 */
1113
1126#if defined(FMC_Bank2_3)
1127#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2) ? \
1128 (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)) : \
1129 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
1130#else
1131#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
1132#endif /* FMC_Bank2_3 */
1133
1146#if defined(FMC_Bank2_3)
1147#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2) ? \
1148 ((__INSTANCE__)->SR2 &= ~(__FLAG__)) : \
1149 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
1150#else
1151#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
1152#endif /* FMC_Bank2_3 */
1153
1157#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
1158
1159#if defined(FMC_Bank4)
1164
1175#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
1176
1187#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
1188
1200#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
1201
1213#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
1214
1218#endif /* FMC_Bank4 */
1219
1220#if defined(FMC_Bank5_6)
1225
1234#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
1235
1244#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
1245
1256#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
1257
1266#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
1267
1271#endif /* FMC_Bank5_6 */
1275
1279
1280/* Private functions ---------------------------------------------------------*/
1284
1285#if defined(FMC_Bank1)
1292HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,
1293 const FMC_NORSRAM_InitTypeDef *Init);
1294HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,
1295 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1296HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,
1297 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
1298 uint32_t ExtendedMode);
1299HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,
1300 FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1304
1308HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1309HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1316#endif /* FMC_Bank1 */
1317
1318#if defined(FMC_Bank3) || defined(FMC_Bank2_3)
1325HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init);
1326HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,
1327 const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1328HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,
1329 const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1330HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1334
1338HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1339HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1340HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
1341 uint32_t Timeout);
1348#endif /* FMC_Bank3) || defined(FMC_Bank2_3 */
1349
1350#if defined(FMC_Bank4)
1357HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, const FMC_PCCARD_InitTypeDef *Init);
1358HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
1359 const FMC_NAND_PCC_TimingTypeDef *Timing);
1360HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
1361 const FMC_NAND_PCC_TimingTypeDef *Timing);
1362HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device,
1363 const FMC_NAND_PCC_TimingTypeDef *Timing);
1364HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
1371#endif /* FMC_Bank4 */
1372
1373#if defined(FMC_Bank5_6)
1380HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init);
1381HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,
1382 const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
1383HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1387
1391HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1392HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1393HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
1394 const FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
1395HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
1396HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
1397 uint32_t AutoRefreshNumber);
1398uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1405#endif /* FMC_Bank5_6 */
1406
1410
1414
1418
1419#ifdef __cplusplus
1420}
1421#endif
1422
1423#endif /* STM32F4xx_LL_FMC_H */
FMC_NAND_TypeDef
#define FMC_NAND_TypeDef
Definition stm32f4xx_ll_fmc.h:203
FMC_NORSRAM_TimingTypeDef
#define FMC_NORSRAM_TimingTypeDef
Definition stm32f4xx_ll_fsmc.h:669
FMC_NORSRAM_DeInit
#define FMC_NORSRAM_DeInit
Definition stm32f4xx_ll_fsmc.h:674
FMC_NORSRAM_TypeDef
#define FMC_NORSRAM_TypeDef
Definition stm32f4xx_ll_fsmc.h:666
FMC_NORSRAM_Timing_Init
#define FMC_NORSRAM_Timing_Init
Definition stm32f4xx_ll_fsmc.h:672
FMC_NORSRAM_EXTENDED_TypeDef
#define FMC_NORSRAM_EXTENDED_TypeDef
Definition stm32f4xx_ll_fsmc.h:667
FMC_NORSRAM_WriteOperation_Disable
#define FMC_NORSRAM_WriteOperation_Disable
Definition stm32f4xx_ll_fsmc.h:676
FMC_NORSRAM_WriteOperation_Enable
#define FMC_NORSRAM_WriteOperation_Enable
Definition stm32f4xx_ll_fsmc.h:675
FMC_NORSRAM_Extended_Timing_Init
#define FMC_NORSRAM_Extended_Timing_Init
Definition stm32f4xx_ll_fsmc.h:673
FMC_NORSRAM_InitTypeDef
#define FMC_NORSRAM_InitTypeDef
Definition stm32f4xx_ll_fsmc.h:668
FMC_NORSRAM_Init
#define FMC_NORSRAM_Init
Definition stm32f4xx_ll_fsmc.h:671
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition stm32f4xx_hal_def.h:39