STM32F4xx HAL Driver master
STM32CubeF4 HAL / LL Drivers API Reference
Loading...
Searching...
No Matches
stm32f4xx_ll_fsmc.h
Go to the documentation of this file.
1
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32F4xx_LL_FSMC_H
21#define STM32F4xx_LL_FSMC_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f4xx_hal_def.h"
29
33
37
41#if defined(FSMC_Bank1)
42
43#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \
44 ((__BANK__) == FSMC_NORSRAM_BANK2) || \
45 ((__BANK__) == FSMC_NORSRAM_BANK3) || \
46 ((__BANK__) == FSMC_NORSRAM_BANK4))
47#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
48 ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
49#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
50 ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
51 ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
52#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \
53 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
54 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
55#define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \
56 ((__SIZE__) == FSMC_PAGE_SIZE_128) || \
57 ((__SIZE__) == FSMC_PAGE_SIZE_256) || \
58 ((__SIZE__) == FSMC_PAGE_SIZE_512) || \
59 ((__SIZE__) == FSMC_PAGE_SIZE_1024))
60#if defined(FSMC_BCR1_WFDIS)
61#define IS_FSMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FSMC_WRITE_FIFO_DISABLE) || \
62 ((__FIFO__) == FSMC_WRITE_FIFO_ENABLE))
63#endif /* FSMC_BCR1_WFDIS */
64#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
65 ((__MODE__) == FSMC_ACCESS_MODE_B) || \
66 ((__MODE__) == FSMC_ACCESS_MODE_C) || \
67 ((__MODE__) == FSMC_ACCESS_MODE_D))
68#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
69 ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
70#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
71 ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
72#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
73 ((__MODE__) == FSMC_WRAP_MODE_ENABLE))
74#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
75 ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS))
76#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
77 ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))
78#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
79 ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE))
80#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
81 ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
82#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
83 ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
84#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
85#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
86 ((__BURST__) == FSMC_WRITE_BURST_ENABLE))
87#define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
88 ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
89#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
90#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
91#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
92#define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)
93#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
94#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))
95#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
96#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
97
98#endif /* FSMC_Bank1 */
99#if defined(FSMC_Bank2_3)
100
101#define IS_FSMC_NAND_BANK(__BANK__) (((__BANK__) == FSMC_NAND_BANK2) || \
102 ((__BANK__) == FSMC_NAND_BANK3))
103#define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \
104 ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE))
105#define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \
106 ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16))
107#define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \
108 ((__STATE__) == FSMC_NAND_ECC_ENABLE))
109
110#define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
111 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
112 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
113 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
114 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
115 ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE))
116#define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)
117#define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)
118#define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)
119#define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)
120#define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)
121#define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)
122#define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE)
123
124#endif /* FSMC_Bank2_3 */
125#if defined(FSMC_Bank4)
126#define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE)
127
128#endif /* FSMC_Bank4 */
129
133
134/* Exported typedef ----------------------------------------------------------*/
135
139
140#if defined(FSMC_Bank1)
141#define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef
142#define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef
143#endif /* FSMC_Bank1 */
144#if defined(FSMC_Bank2_3)
145#define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef
146#endif /* FSMC_Bank2_3 */
147#if defined(FSMC_Bank4)
148#define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef
149#endif /* FSMC_Bank4 */
150
151#if defined(FSMC_Bank1)
152#define FSMC_NORSRAM_DEVICE FSMC_Bank1
153#define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E
154#endif /* FSMC_Bank1 */
155#if defined(FSMC_Bank2_3)
156#define FSMC_NAND_DEVICE FSMC_Bank2_3
157#endif /* FSMC_Bank2_3 */
158#if defined(FSMC_Bank4)
159#define FSMC_PCCARD_DEVICE FSMC_Bank4
160#endif /* FSMC_Bank4 */
161
162#if defined(FSMC_Bank1)
166typedef struct
167{
168 uint32_t NSBank;
170
171 uint32_t DataAddressMux;
174
175 uint32_t MemoryType;
178
179 uint32_t MemoryDataWidth;
181
182 uint32_t BurstAccessMode;
185
186 uint32_t WaitSignalPolarity;
189
190 uint32_t WrapMode;
194
195 uint32_t WaitSignalActive;
199
200 uint32_t WriteOperation;
203
204 uint32_t WaitSignal;
207
208 uint32_t ExtendedMode;
210
211 uint32_t AsynchronousWait;
214
215 uint32_t WriteBurst;
217
218 uint32_t ContinuousClock;
223
224 uint32_t WriteFifo;
229
230 uint32_t PageSize;
232} FSMC_NORSRAM_InitTypeDef;
233
237typedef struct
238{
239 uint32_t AddressSetupTime;
243
244 uint32_t AddressHoldTime;
248
249 uint32_t DataSetupTime;
254
255 uint32_t BusTurnAroundDuration;
259
260 uint32_t CLKDivision;
265
266 uint32_t DataLatency;
273
274 uint32_t AccessMode;
276} FSMC_NORSRAM_TimingTypeDef;
277#endif /* FSMC_Bank1 */
278
279#if defined(FSMC_Bank2_3)
283typedef struct
284{
285 uint32_t NandBank;
287
288 uint32_t Waitfeature;
290
291 uint32_t MemoryDataWidth;
293
294 uint32_t EccComputation;
296
297 uint32_t ECCPageSize;
299
300 uint32_t TCLRSetupTime;
303
304 uint32_t TARSetupTime;
307} FSMC_NAND_InitTypeDef;
308#endif /* FSMC_Bank2_3 */
309
310#if defined(FSMC_Bank2_3) || defined(FSMC_Bank4)
314typedef struct
315{
316 uint32_t SetupTime;
321
322 uint32_t WaitSetupTime;
327
328 uint32_t HoldSetupTime;
334
335 uint32_t HiZSetupTime;
340} FSMC_NAND_PCC_TimingTypeDef;
341#endif /* FSMC_Bank2_3 */
342
343#if defined(FSMC_Bank4)
347typedef struct
348{
349 uint32_t Waitfeature;
351
352 uint32_t TCLRSetupTime;
355
356 uint32_t TARSetupTime;
359} FSMC_PCCARD_InitTypeDef;
360#endif /* FSMC_Bank4 */
361
365
366/* Exported constants --------------------------------------------------------*/
370#if defined(FSMC_Bank1)
371
375
379#define FSMC_NORSRAM_BANK1 (0x00000000U)
380#define FSMC_NORSRAM_BANK2 (0x00000002U)
381#define FSMC_NORSRAM_BANK3 (0x00000004U)
382#define FSMC_NORSRAM_BANK4 (0x00000006U)
386
390#define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U)
391#define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U)
395
399#define FSMC_MEMORY_TYPE_SRAM (0x00000000U)
400#define FSMC_MEMORY_TYPE_PSRAM (0x00000004U)
401#define FSMC_MEMORY_TYPE_NOR (0x00000008U)
405
409#define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U)
410#define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U)
411#define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U)
415
419#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U)
420#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U)
424
428#define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U)
429#define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U)
433
437#define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U)
438#define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U)
442
447#define FSMC_WRAP_MODE_DISABLE (0x00000000U)
448#define FSMC_WRAP_MODE_ENABLE (0x00000400U)
452
456#define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U)
457#define FSMC_WAIT_TIMING_DURING_WS (0x00000800U)
461
465#define FSMC_WRITE_OPERATION_DISABLE (0x00000000U)
466#define FSMC_WRITE_OPERATION_ENABLE (0x00001000U)
470
474#define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U)
475#define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U)
479
483#define FSMC_EXTENDED_MODE_DISABLE (0x00000000U)
484#define FSMC_EXTENDED_MODE_ENABLE (0x00004000U)
488
492#define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U)
493#define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U)
497
501#define FSMC_PAGE_SIZE_NONE (0x00000000U)
502#define FSMC_PAGE_SIZE_128 FSMC_BCR1_CPSIZE_0
503#define FSMC_PAGE_SIZE_256 FSMC_BCR1_CPSIZE_1
504#define FSMC_PAGE_SIZE_512 (FSMC_BCR1_CPSIZE_0\
505 | FSMC_BCR1_CPSIZE_1)
506#define FSMC_PAGE_SIZE_1024 FSMC_BCR1_CPSIZE_2
510
514#define FSMC_WRITE_BURST_DISABLE (0x00000000U)
515#define FSMC_WRITE_BURST_ENABLE (0x00080000U)
519
524#define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U)
525#define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U)
529
530#if defined(FSMC_BCR1_WFDIS)
535#define FSMC_WRITE_FIFO_DISABLE FSMC_BCR1_WFDIS
536#define FSMC_WRITE_FIFO_ENABLE (0x00000000U)
537#endif /* FSMC_BCR1_WFDIS */
541
545#define FSMC_ACCESS_MODE_A (0x00000000U)
546#define FSMC_ACCESS_MODE_B (0x10000000U)
547#define FSMC_ACCESS_MODE_C (0x20000000U)
548#define FSMC_ACCESS_MODE_D (0x30000000U)
552
556#endif /* FSMC_Bank1 */
557
558#if defined(FSMC_Bank2_3) || defined(FSMC_Bank4)
559
566#if defined(FSMC_Bank2_3)
567#define FSMC_NAND_BANK2 (0x00000010U)
568#endif /* FSMC_Bank2_3 */
569#define FSMC_NAND_BANK3 (0x00000100U)
573
577#define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U)
578#define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U)
582
586#if defined(FSMC_Bank4)
587#define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U)
588#endif /* FSMC_Bank4 */
589#define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U)
593
597#define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U)
598#define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U)
602
606#define FSMC_NAND_ECC_DISABLE (0x00000000U)
607#define FSMC_NAND_ECC_ENABLE (0x00000040U)
611
615#define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U)
616#define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U)
617#define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U)
618#define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U)
619#define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U)
620#define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U)
624
628#endif /* FSMC_Bank2_3 || FSMC_Bank4 */
629
630
634#if defined(FSMC_Bank2_3) || defined(FSMC_Bank4)
635#define FSMC_IT_RISING_EDGE (0x00000008U)
636#define FSMC_IT_LEVEL (0x00000010U)
637#define FSMC_IT_FALLING_EDGE (0x00000020U)
638#endif /* FSMC_Bank2_3 || FSMC_Bank4 */
642
646#if defined(FSMC_Bank2_3) || defined(FSMC_Bank4)
647#define FSMC_FLAG_RISING_EDGE (0x00000001U)
648#define FSMC_FLAG_LEVEL (0x00000002U)
649#define FSMC_FLAG_FALLING_EDGE (0x00000004U)
650#define FSMC_FLAG_FEMPT (0x00000040U)
651#endif /* FSMC_Bank2_3 || FSMC_Bank4 */
655
659#define FMC_WRITE_OPERATION_DISABLE FSMC_WRITE_OPERATION_DISABLE
660#define FMC_WRITE_OPERATION_ENABLE FSMC_WRITE_OPERATION_ENABLE
661
662#define FMC_NORSRAM_MEM_BUS_WIDTH_8 FSMC_NORSRAM_MEM_BUS_WIDTH_8
663#define FMC_NORSRAM_MEM_BUS_WIDTH_16 FSMC_NORSRAM_MEM_BUS_WIDTH_16
664#define FMC_NORSRAM_MEM_BUS_WIDTH_32 FSMC_NORSRAM_MEM_BUS_WIDTH_32
665
666#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
667#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
668#define FMC_NORSRAM_InitTypeDef FSMC_NORSRAM_InitTypeDef
669#define FMC_NORSRAM_TimingTypeDef FSMC_NORSRAM_TimingTypeDef
670
671#define FMC_NORSRAM_Init FSMC_NORSRAM_Init
672#define FMC_NORSRAM_Timing_Init FSMC_NORSRAM_Timing_Init
673#define FMC_NORSRAM_Extended_Timing_Init FSMC_NORSRAM_Extended_Timing_Init
674#define FMC_NORSRAM_DeInit FSMC_NORSRAM_DeInit
675#define FMC_NORSRAM_WriteOperation_Enable FSMC_NORSRAM_WriteOperation_Enable
676#define FMC_NORSRAM_WriteOperation_Disable FSMC_NORSRAM_WriteOperation_Disable
677
678#define __FMC_NORSRAM_ENABLE __FSMC_NORSRAM_ENABLE
679#define __FMC_NORSRAM_DISABLE __FSMC_NORSRAM_DISABLE
680
681#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
682#define FMC_NAND_InitTypeDef FSMC_NAND_InitTypeDef
683#define FMC_PCCARD_InitTypeDef FSMC_PCCARD_InitTypeDef
684#define FMC_NAND_PCC_TimingTypeDef FSMC_NAND_PCC_TimingTypeDef
685
686#define FMC_NAND_Init FSMC_NAND_Init
687#define FMC_NAND_CommonSpace_Timing_Init FSMC_NAND_CommonSpace_Timing_Init
688#define FMC_NAND_AttributeSpace_Timing_Init FSMC_NAND_AttributeSpace_Timing_Init
689#define FMC_NAND_DeInit FSMC_NAND_DeInit
690#define FMC_NAND_ECC_Enable FSMC_NAND_ECC_Enable
691#define FMC_NAND_ECC_Disable FSMC_NAND_ECC_Disable
692#define FMC_NAND_GetECC FSMC_NAND_GetECC
693#define FMC_PCCARD_Init FSMC_PCCARD_Init
694#define FMC_PCCARD_CommonSpace_Timing_Init FSMC_PCCARD_CommonSpace_Timing_Init
695#define FMC_PCCARD_AttributeSpace_Timing_Init FSMC_PCCARD_AttributeSpace_Timing_Init
696#define FMC_PCCARD_IOSpace_Timing_Init FSMC_PCCARD_IOSpace_Timing_Init
697#define FMC_PCCARD_DeInit FSMC_PCCARD_DeInit
698
699#define __FMC_NAND_ENABLE __FSMC_NAND_ENABLE
700#define __FMC_NAND_DISABLE __FSMC_NAND_DISABLE
701#define __FMC_PCCARD_ENABLE __FSMC_PCCARD_ENABLE
702#define __FMC_PCCARD_DISABLE __FSMC_PCCARD_DISABLE
703#define __FMC_NAND_ENABLE_IT __FSMC_NAND_ENABLE_IT
704#define __FMC_NAND_DISABLE_IT __FSMC_NAND_DISABLE_IT
705#define __FMC_NAND_GET_FLAG __FSMC_NAND_GET_FLAG
706#define __FMC_NAND_CLEAR_FLAG __FSMC_NAND_CLEAR_FLAG
707#define __FMC_PCCARD_ENABLE_IT __FSMC_PCCARD_ENABLE_IT
708#define __FMC_PCCARD_DISABLE_IT __FSMC_PCCARD_DISABLE_IT
709#define __FMC_PCCARD_GET_FLAG __FSMC_PCCARD_GET_FLAG
710#define __FMC_PCCARD_CLEAR_FLAG __FSMC_PCCARD_CLEAR_FLAG
711#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
712
713#define FMC_NORSRAM_TypeDef FSMC_NORSRAM_TypeDef
714#define FMC_NORSRAM_EXTENDED_TypeDef FSMC_NORSRAM_EXTENDED_TypeDef
715#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
716#define FMC_NAND_TypeDef FSMC_NAND_TypeDef
717#define FMC_PCCARD_TypeDef FSMC_PCCARD_TypeDef
718#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
719
720#define FMC_NORSRAM_DEVICE FSMC_NORSRAM_DEVICE
721#define FMC_NORSRAM_EXTENDED_DEVICE FSMC_NORSRAM_EXTENDED_DEVICE
722#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
723#define FMC_NAND_DEVICE FSMC_NAND_DEVICE
724#define FMC_PCCARD_DEVICE FSMC_PCCARD_DEVICE
725
726#define FMC_NAND_BANK2 FSMC_NAND_BANK2
727#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
728
729#define FMC_NORSRAM_BANK1 FSMC_NORSRAM_BANK1
730#define FMC_NORSRAM_BANK2 FSMC_NORSRAM_BANK2
731#define FMC_NORSRAM_BANK3 FSMC_NORSRAM_BANK3
732
733#define FMC_IT_RISING_EDGE FSMC_IT_RISING_EDGE
734#define FMC_IT_LEVEL FSMC_IT_LEVEL
735#define FMC_IT_FALLING_EDGE FSMC_IT_FALLING_EDGE
736#define FMC_IT_REFRESH_ERROR FSMC_IT_REFRESH_ERROR
737
738#define FMC_FLAG_RISING_EDGE FSMC_FLAG_RISING_EDGE
739#define FMC_FLAG_LEVEL FSMC_FLAG_LEVEL
740#define FMC_FLAG_FALLING_EDGE FSMC_FLAG_FALLING_EDGE
741#define FMC_FLAG_FEMPT FSMC_FLAG_FEMPT
745
749
753
754/* Private macro -------------------------------------------------------------*/
758#if defined(FSMC_Bank1)
763
770#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
771 |= FSMC_BCR1_MBKEN)
772
779#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\
780 &= ~FSMC_BCR1_MBKEN)
781
785#endif /* FSMC_Bank1 */
786
787#if defined(FSMC_Bank2_3)
792
799#define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2) ? \
800 ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN) : \
801 ((__INSTANCE__)->PCR3 |= FSMC_PCR3_PBKEN))
802
809#define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2) ? \
810 CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCR2_PBKEN) : \
811 CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCR3_PBKEN))
812
816#endif /* FSMC_Bank2_3 */
817
818#if defined(FSMC_Bank4)
828#define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN)
829
835#define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN)
839
840#endif /* FSMC_Bank4 */
841#if defined(FSMC_Bank2_3)
846
858#define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2) ? \
859 ((__INSTANCE__)->SR2 |= (__INTERRUPT__)) : \
860 ((__INSTANCE__)->SR3 |= (__INTERRUPT__)))
861
873#define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2) ? \
874 ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)) : \
875 ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
876
889#define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2) ? \
890 (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)) : \
891 (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
892
905#define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2) ? \
906 ((__INSTANCE__)->SR2 &= ~(__FLAG__)) : \
907 ((__INSTANCE__)->SR3 &= ~(__FLAG__)))
908
912#endif /* FSMC_Bank2_3 */
913
914#if defined(FSMC_Bank4)
919
930#define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__))
931
942#define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
943
955#define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
956
968#define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
969
973#endif /* FSMC_Bank4 */
974
978
982
983/* Private functions ---------------------------------------------------------*/
987
988#if defined(FSMC_Bank1)
995HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
996 const FSMC_NORSRAM_InitTypeDef *Init);
997HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
998 const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
999HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
1000 const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
1001 uint32_t ExtendedMode);
1002HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
1003 FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1007
1011HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1012HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1019#endif /* FSMC_Bank1 */
1020
1021#if defined(FSMC_Bank2_3)
1028HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, const FSMC_NAND_InitTypeDef *Init);
1029HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
1030 const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1031HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
1032 const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1033HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank);
1037
1041HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
1042HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank);
1043HAL_StatusTypeDef FSMC_NAND_GetECC(const FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
1044 uint32_t Timeout);
1051#endif /* FSMC_Bank2_3 */
1052
1053#if defined(FSMC_Bank4)
1060HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, const FSMC_PCCARD_InitTypeDef *Init);
1061HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
1062 const FSMC_NAND_PCC_TimingTypeDef *Timing);
1063HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
1064 const FSMC_NAND_PCC_TimingTypeDef *Timing);
1065HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
1066 const FSMC_NAND_PCC_TimingTypeDef *Timing);
1067HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device);
1074#endif /* FSMC_Bank4 */
1075
1076
1080
1084
1088
1089#ifdef __cplusplus
1090}
1091#endif
1092
1093#endif /* STM32F4xx_LL_FSMC_H */
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition stm32f4xx_hal_def.h:39