RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral: More...

#include "stm32f4xx_hal.h"

Include dependency graph for stm32f4xx_hal_rcc.c:

Detailed Description

RCC HAL module driver. This file provides firmware functions to manage the following functionalities of the Reset and Clock Control (RCC) peripheral:

Author

MCD Application Team

Initialization and de-initialization functions
Peripheral Control functions

==============================================================================
                    ##### RCC specific features #####
==============================================================================
  [..]
    After reset the device is running from Internal High Speed oscillator
    (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
    and I-Cache are disabled, and all peripherals are off except internal
    SRAM, Flash and JTAG.
    (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
        all peripherals mapped on these busses are running at HSI speed.
    (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
    (+) All GPIOs are in input floating state, except the JTAG pins which
        are assigned to be used for debug purpose.

  [..]
    Once the device started from reset, the user application has to:
    (+) Configure the clock source to be used to drive the System clock
        (if the application needs higher frequency/performance)
    (+) Configure the System clock frequency and Flash settings
    (+) Configure the AHB and APB busses prescalers
    (+) Enable the clock for the peripheral(s) to be used
    (+) Configure the clock source(s) for peripherals which clocks are not
        derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)

                    ##### RCC Limitations #####
==============================================================================
  [..]
    A delay between an RCC peripheral clock enable and the effective peripheral
    enabling should be taken into account in order to manage the peripheral read/write
    from/to registers.
    (+) This delay depends on the peripheral mapping.
    (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
        after the clock enable bit is set on the hardware register
    (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
        after the clock enable bit is set on the hardware register

  [..]
    Implemented Workaround:
    (+) For AHB & APB peripherals, a dummy read to the peripheral register has been
        inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.

Attention

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Definition in file stm32f4xx_hal_rcc.c.