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STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_ll_usart.h
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1
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef __STM32F4xx_LL_USART_H
21#define __STM32F4xx_LL_USART_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f4xx.h"
29
33
34#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (UART10)
35
39
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42
43/* Private constants ---------------------------------------------------------*/
47
48/* Defines used for the bit position in the register and perform offsets*/
49#define USART_POSITION_GTPR_GT USART_GTPR_GT_Pos
53
54/* Private macros ------------------------------------------------------------*/
55#if defined(USE_FULL_LL_DRIVER)
62#endif /*USE_FULL_LL_DRIVER*/
63
64/* Exported types ------------------------------------------------------------*/
65#if defined(USE_FULL_LL_DRIVER)
69
73typedef struct
74{
75 uint32_t BaudRate;
78
79 uint32_t DataWidth;
83
84 uint32_t StopBits;
88
89 uint32_t Parity;
93
94 uint32_t TransferDirection;
98
99 uint32_t HardwareFlowControl;
103
104 uint32_t OverSampling;
108
109} LL_USART_InitTypeDef;
110
114typedef struct
115{
116 uint32_t ClockOutput;
122
123 uint32_t ClockPolarity;
128
129 uint32_t ClockPhase;
134
135 uint32_t LastBitClockPulse;
141
142} LL_USART_ClockInitTypeDef;
143
147#endif /* USE_FULL_LL_DRIVER */
148
149/* Exported constants --------------------------------------------------------*/
153
158#define LL_USART_SR_PE USART_SR_PE
159#define LL_USART_SR_FE USART_SR_FE
160#define LL_USART_SR_NE USART_SR_NE
161#define LL_USART_SR_ORE USART_SR_ORE
162#define LL_USART_SR_IDLE USART_SR_IDLE
163#define LL_USART_SR_RXNE USART_SR_RXNE
164#define LL_USART_SR_TC USART_SR_TC
165#define LL_USART_SR_TXE USART_SR_TXE
166#define LL_USART_SR_LBD USART_SR_LBD
167#define LL_USART_SR_CTS USART_SR_CTS
171
176#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE
177#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE
178#define LL_USART_CR1_TCIE USART_CR1_TCIE
179#define LL_USART_CR1_TXEIE USART_CR1_TXEIE
180#define LL_USART_CR1_PEIE USART_CR1_PEIE
181#define LL_USART_CR2_LBDIE USART_CR2_LBDIE
182#define LL_USART_CR3_EIE USART_CR3_EIE
183#define LL_USART_CR3_CTSIE USART_CR3_CTSIE
187
191#define LL_USART_DIRECTION_NONE 0x00000000U
192#define LL_USART_DIRECTION_RX USART_CR1_RE
193#define LL_USART_DIRECTION_TX USART_CR1_TE
194#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE)
198
202#define LL_USART_PARITY_NONE 0x00000000U
203#define LL_USART_PARITY_EVEN USART_CR1_PCE
204#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS)
208
212#define LL_USART_WAKEUP_IDLELINE 0x00000000U
213#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE
217
221#define LL_USART_DATAWIDTH_8B 0x00000000U
222#define LL_USART_DATAWIDTH_9B USART_CR1_M
226
230#define LL_USART_OVERSAMPLING_16 0x00000000U
231#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8
235
236#if defined(USE_FULL_LL_DRIVER)
240
241#define LL_USART_CLOCK_DISABLE 0x00000000U
242#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN
246#endif /*USE_FULL_LL_DRIVER*/
247
251#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U
252#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL
256
260#define LL_USART_PHASE_1EDGE 0x00000000U
261#define LL_USART_PHASE_2EDGE USART_CR2_CPHA
265
269#define LL_USART_POLARITY_LOW 0x00000000U
270#define LL_USART_POLARITY_HIGH USART_CR2_CPOL
274
278#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0
279#define LL_USART_STOPBITS_1 0x00000000U
280#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
281#define LL_USART_STOPBITS_2 USART_CR2_STOP_1
285
289#define LL_USART_HWCONTROL_NONE 0x00000000U
290#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE
291#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE
292#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
296
300#define LL_USART_IRDA_POWER_NORMAL 0x00000000U
301#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP
305
309#define LL_USART_LINBREAK_DETECT_10B 0x00000000U
310#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL
314
318
319/* Exported macro ------------------------------------------------------------*/
323
327
335#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
336
343#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
347
351
359#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(2*((uint64_t)(__BAUDRATE__)))))
360#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100)
361#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8)\
362 + 50) / 100)
363/* UART BRR = mantissa + overflow + fraction
364 = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */
365#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
366 ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \
367 (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07))
368
376#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) ((uint32_t)((((uint64_t)(__PERIPHCLK__))*25)/(4*((uint64_t)(__BAUDRATE__)))))
377#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100)
378#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) ((((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16)\
379 + 50) / 100)
380/* USART BRR = mantissa + overflow + fraction
381 = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */
382#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \
383 (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \
384 (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F))
385
389
393
394/* Exported functions --------------------------------------------------------*/
395
399
403
410__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
411{
412 SET_BIT(USARTx->CR1, USART_CR1_UE);
413}
414
424__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
425{
426 CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
427}
428
435__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx)
436{
437 return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE));
438}
439
446__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
447{
448 ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
449}
450
457__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
458{
459 ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
460}
461
468__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
469{
470 ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
471}
472
479__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
480{
481 ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
482}
483
497__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
498{
499 ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
500}
501
513__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx)
514{
515 return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
516}
517
532__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
533{
534 MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
535}
536
547__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx)
548{
549 return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
550}
551
561__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
562{
563 MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
564}
565
574__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx)
575{
576 return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
577}
578
588__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
589{
590 MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
591}
592
601__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx)
602{
603 return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
604}
605
615__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
616{
617 MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
618}
619
628__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx)
629{
630 return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
631}
632
644__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
645{
646 MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
647}
648
660__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx)
661{
662 return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
663}
664
676__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
677{
678 MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
679}
680
691__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx)
692{
693 return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
694}
695
707__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
708{
709 MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
710}
711
722__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx)
723{
724 return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
725}
726
750__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
751{
752 MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
753}
754
763__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
764{
765 SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
766}
767
776__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
777{
778 CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
779}
780
789__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx)
790{
791 return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN));
792}
793
805__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
806{
807 MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
808}
809
820__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx)
821{
822 return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
823}
824
850__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
851 uint32_t StopBits)
852{
853 MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
854 MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
855}
856
866__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress)
867{
868 MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD));
869}
870
878__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx)
879{
880 return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD));
881}
882
891__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
892{
893 SET_BIT(USARTx->CR3, USART_CR3_RTSE);
894}
895
904__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
905{
906 CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
907}
908
917__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
918{
919 SET_BIT(USARTx->CR3, USART_CR3_CTSE);
920}
921
930__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
931{
932 CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
933}
934
949__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
950{
951 MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
952}
953
967__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx)
968{
969 return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
970}
971
978__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
979{
980 SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
981}
982
989__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
990{
991 CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
992}
993
1000__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx)
1001{
1002 return (READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT));
1003}
1004
1020__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling,
1021 uint32_t BaudRate)
1022{
1023 if (OverSampling == LL_USART_OVERSAMPLING_8)
1024 {
1025 USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate));
1026 }
1027 else
1028 {
1029 USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate));
1030 }
1031}
1032
1045__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling)
1046{
1047 uint32_t usartdiv = 0x0U;
1048 uint32_t brrresult = 0x0U;
1049
1050 usartdiv = USARTx->BRR;
1051
1052 if (OverSampling == LL_USART_OVERSAMPLING_8)
1053 {
1054 if ((usartdiv & 0xFFF7U) != 0U)
1055 {
1056 usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
1057 brrresult = (PeriphClk * 2U) / usartdiv;
1058 }
1059 }
1060 else
1061 {
1062 if ((usartdiv & 0xFFFFU) != 0U)
1063 {
1064 brrresult = PeriphClk / usartdiv;
1065 }
1066 }
1067 return (brrresult);
1068}
1069
1073
1077
1086__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
1087{
1088 SET_BIT(USARTx->CR3, USART_CR3_IREN);
1089}
1090
1099__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
1100{
1101 CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
1102}
1103
1112__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx)
1113{
1114 return (READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN));
1115}
1116
1128__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
1129{
1130 MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
1131}
1132
1143__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx)
1144{
1145 return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
1146}
1147
1158__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
1159{
1160 MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
1161}
1162
1172__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx)
1173{
1174 return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
1175}
1176
1180
1184
1193__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
1194{
1195 SET_BIT(USARTx->CR3, USART_CR3_NACK);
1196}
1197
1206__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
1207{
1208 CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
1209}
1210
1219__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx)
1220{
1221 return (READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK));
1222}
1223
1232__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
1233{
1234 SET_BIT(USARTx->CR3, USART_CR3_SCEN);
1235}
1236
1245__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
1246{
1247 CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
1248}
1249
1258__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx)
1259{
1260 return (READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN));
1261}
1262
1273__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
1274{
1275 MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, PrescalerValue);
1276}
1277
1287__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx)
1288{
1289 return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
1290}
1291
1302__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
1303{
1304 MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, GuardTime << USART_POSITION_GTPR_GT);
1305}
1306
1316__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx)
1317{
1318 return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_POSITION_GTPR_GT);
1319}
1320
1324
1328
1337__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
1338{
1339 SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
1340}
1341
1350__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
1351{
1352 CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
1353}
1354
1363__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx)
1364{
1365 return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL));
1366}
1367
1371
1375
1387__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
1388{
1389 MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
1390}
1391
1402__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx)
1403{
1404 return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
1405}
1406
1415__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
1416{
1417 SET_BIT(USARTx->CR2, USART_CR2_LINEN);
1418}
1419
1428__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
1429{
1430 CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
1431}
1432
1441__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx)
1442{
1443 return (READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN));
1444}
1445
1449
1453
1479__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
1480{
1481 /* In Asynchronous mode, the following bits must be kept cleared:
1482 - LINEN, CLKEN bits in the USART_CR2 register,
1483 - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
1484 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
1485 CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
1486}
1487
1515__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
1516{
1517 /* In Synchronous mode, the following bits must be kept cleared:
1518 - LINEN bit in the USART_CR2 register,
1519 - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/
1520 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
1521 CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
1522 /* set the UART/USART in Synchronous mode */
1523 SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
1524}
1525
1555__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
1556{
1557 /* In LIN mode, the following bits must be kept cleared:
1558 - STOP and CLKEN bits in the USART_CR2 register,
1559 - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
1560 CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
1561 CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
1562 /* Set the UART/USART in LIN mode */
1563 SET_BIT(USARTx->CR2, USART_CR2_LINEN);
1564}
1565
1593__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
1594{
1595 /* In Half Duplex mode, the following bits must be kept cleared:
1596 - LINEN and CLKEN bits in the USART_CR2 register,
1597 - SCEN and IREN bits in the USART_CR3 register.*/
1598 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
1599 CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
1600 /* set the UART/USART in Half Duplex mode */
1601 SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
1602}
1603
1633__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
1634{
1635 /* In Smartcard mode, the following bits must be kept cleared:
1636 - LINEN bit in the USART_CR2 register,
1637 - IREN and HDSEL bits in the USART_CR3 register.*/
1638 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
1639 CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
1640 /* Configure Stop bits to 1.5 bits */
1641 /* Synchronous mode is activated by default */
1642 SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
1643 /* set the UART/USART in Smartcard mode */
1644 SET_BIT(USARTx->CR3, USART_CR3_SCEN);
1645}
1646
1676__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
1677{
1678 /* In IRDA mode, the following bits must be kept cleared:
1679 - LINEN, STOP and CLKEN bits in the USART_CR2 register,
1680 - SCEN and HDSEL bits in the USART_CR3 register.*/
1681 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
1682 CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
1683 /* set the UART/USART in IRDA mode */
1684 SET_BIT(USARTx->CR3, USART_CR3_IREN);
1685}
1686
1714__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
1715{
1716 /* In Multi Processor mode, the following bits must be kept cleared:
1717 - LINEN and CLKEN bits in the USART_CR2 register,
1718 - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/
1719 CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
1720 CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
1721}
1722
1726
1730
1737__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx)
1738{
1739 return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE));
1740}
1741
1748__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx)
1749{
1750 return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE));
1751}
1752
1759__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx)
1760{
1761 return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE));
1762}
1763
1770__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx)
1771{
1772 return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE));
1773}
1774
1781__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx)
1782{
1783 return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE));
1784}
1785
1792__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(const USART_TypeDef *USARTx)
1793{
1794 return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE));
1795}
1796
1803__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx)
1804{
1805 return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC));
1806}
1807
1814__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(const USART_TypeDef *USARTx)
1815{
1816 return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE));
1817}
1818
1827__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx)
1828{
1829 return (READ_BIT(USARTx->SR, USART_SR_LBD) == (USART_SR_LBD));
1830}
1831
1840__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx)
1841{
1842 return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS));
1843}
1844
1851__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx)
1852{
1853 return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK));
1854}
1855
1862__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx)
1863{
1864 return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU));
1865}
1866
1877__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
1878{
1879 __IO uint32_t tmpreg;
1880 tmpreg = USARTx->SR;
1881 (void) tmpreg;
1882 tmpreg = USARTx->DR;
1883 (void) tmpreg;
1884}
1885
1896__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
1897{
1898 __IO uint32_t tmpreg;
1899 tmpreg = USARTx->SR;
1900 (void) tmpreg;
1901 tmpreg = USARTx->DR;
1902 (void) tmpreg;
1903}
1904
1915__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
1916{
1917 __IO uint32_t tmpreg;
1918 tmpreg = USARTx->SR;
1919 (void) tmpreg;
1920 tmpreg = USARTx->DR;
1921 (void) tmpreg;
1922}
1923
1934__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
1935{
1936 __IO uint32_t tmpreg;
1937 tmpreg = USARTx->SR;
1938 (void) tmpreg;
1939 tmpreg = USARTx->DR;
1940 (void) tmpreg;
1941}
1942
1953__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
1954{
1955 __IO uint32_t tmpreg;
1956 tmpreg = USARTx->SR;
1957 (void) tmpreg;
1958 tmpreg = USARTx->DR;
1959 (void) tmpreg;
1960}
1961
1968__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
1969{
1970 WRITE_REG(USARTx->SR, ~(USART_SR_TC));
1971}
1972
1979__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx)
1980{
1981 WRITE_REG(USARTx->SR, ~(USART_SR_RXNE));
1982}
1983
1992__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
1993{
1994 WRITE_REG(USARTx->SR, ~(USART_SR_LBD));
1995}
1996
2005__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
2006{
2007 WRITE_REG(USARTx->SR, ~(USART_SR_CTS));
2008}
2009
2013
2017
2024__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
2025{
2026 ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
2027}
2028
2035__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx)
2036{
2037 ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE);
2038}
2039
2046__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
2047{
2048 ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
2049}
2050
2057__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx)
2058{
2059 ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE);
2060}
2061
2068__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
2069{
2070 ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
2071}
2072
2081__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
2082{
2083 SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
2084}
2085
2096__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
2097{
2098 ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
2099}
2100
2109__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
2110{
2111 ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
2112}
2113
2120__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
2121{
2122 ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
2123}
2124
2131__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx)
2132{
2133 ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE);
2134}
2135
2142__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
2143{
2144 ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
2145}
2146
2153__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx)
2154{
2155 ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE);
2156}
2157
2164__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
2165{
2166 ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
2167}
2168
2177__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
2178{
2179 CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
2180}
2181
2192__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
2193{
2194 ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
2195}
2196
2205__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
2206{
2207 ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
2208}
2209
2216__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx)
2217{
2218 return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE));
2219}
2220
2227__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(const USART_TypeDef *USARTx)
2228{
2229 return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE));
2230}
2231
2238__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx)
2239{
2240 return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE));
2241}
2242
2249__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(const USART_TypeDef *USARTx)
2250{
2251 return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE));
2252}
2253
2260__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx)
2261{
2262 return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE));
2263}
2264
2273__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx)
2274{
2275 return (READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE));
2276}
2277
2284__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx)
2285{
2286 return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE));
2287}
2288
2297__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx)
2298{
2299 return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE));
2300}
2301
2305
2309
2316__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
2317{
2318 ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
2319}
2320
2327__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
2328{
2329 ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
2330}
2331
2338__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx)
2339{
2340 return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR));
2341}
2342
2349__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
2350{
2351 ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
2352}
2353
2360__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
2361{
2362 ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
2363}
2364
2371__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx)
2372{
2373 return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT));
2374}
2375
2383__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx)
2384{
2385 /* return address of DR register */
2386 return ((uint32_t) &(USARTx->DR));
2387}
2388
2392
2396
2403__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx)
2404{
2405 return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR));
2406}
2407
2414__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx)
2415{
2416 return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR));
2417}
2418
2426__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
2427{
2428 USARTx->DR = Value;
2429}
2430
2438__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
2439{
2440 USARTx->DR = Value & 0x1FFU;
2441}
2442
2446
2450
2457__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
2458{
2459 SET_BIT(USARTx->CR1, USART_CR1_SBK);
2460}
2461
2468__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
2469{
2470 SET_BIT(USARTx->CR1, USART_CR1_RWU);
2471}
2472
2479__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx)
2480{
2481 CLEAR_BIT(USARTx->CR1, USART_CR1_RWU);
2482}
2483
2487
2488#if defined(USE_FULL_LL_DRIVER)
2492ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx);
2493ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct);
2494void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
2495ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
2496void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
2500#endif /* USE_FULL_LL_DRIVER */
2501
2505
2509
2510#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || UART10 */
2511
2515
2516#ifdef __cplusplus
2517}
2518#endif
2519
2520#endif /* __STM32F4xx_LL_USART_H */
2521