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STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_ll_tim.c
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1
18#if defined(USE_FULL_LL_DRIVER)
19
20/* Includes ------------------------------------------------------------------*/
21#include "stm32f4xx_ll_tim.h"
22#include "stm32f4xx_ll_bus.h"
23
24#ifdef USE_FULL_ASSERT
25#include "stm32_assert.h"
26#else
27#define assert_param(expr) ((void)0U)
28#endif /* USE_FULL_ASSERT */
29
33
34#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14)
35
39
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42/* Private constants ---------------------------------------------------------*/
43/* Private macros ------------------------------------------------------------*/
47#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
48 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
49 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
50 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
51 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
52
53#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
54 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
55 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
56
57#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
58 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
59 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
60 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
61 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
62 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
63 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
64 || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
65
66#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
67 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
68
69#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
70 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
71
72#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
73 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
74
75#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
76 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
77 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
78
79#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
80 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
81 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
82 || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
83
84#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
85 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
86 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
87 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
88 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
89 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
90 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
91 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
92 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
93 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
94 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
95 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
96 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
97 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
98 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
99 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
100
101#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
102 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
103 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
104
105#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
106 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
107 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
108
109#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
110 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
111
112#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
113 || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
114
115#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
116 || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
117
118#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
119 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
120 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
121 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
122
123#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
124 || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
125
126#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
127 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
128
129#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
130 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
134
135
136/* Private function prototypes -----------------------------------------------*/
140static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
141static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
142static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
143static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
144static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
145static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
146static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
147static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
151
152/* Exported functions --------------------------------------------------------*/
156
160
168ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)
169{
170 ErrorStatus result = SUCCESS;
171
172 /* Check the parameters */
173 assert_param(IS_TIM_INSTANCE(TIMx));
174
175 if (TIMx == TIM1)
176 {
177 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
178 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
179 }
180#if defined(TIM2)
181 else if (TIMx == TIM2)
182 {
183 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
184 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
185 }
186#endif /* TIM2 */
187#if defined(TIM3)
188 else if (TIMx == TIM3)
189 {
190 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
191 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
192 }
193#endif /* TIM3 */
194#if defined(TIM4)
195 else if (TIMx == TIM4)
196 {
197 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
198 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
199 }
200#endif /* TIM4 */
201#if defined(TIM5)
202 else if (TIMx == TIM5)
203 {
204 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
205 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
206 }
207#endif /* TIM5 */
208#if defined(TIM6)
209 else if (TIMx == TIM6)
210 {
211 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
212 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
213 }
214#endif /* TIM6 */
215#if defined (TIM7)
216 else if (TIMx == TIM7)
217 {
218 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
219 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
220 }
221#endif /* TIM7 */
222#if defined(TIM8)
223 else if (TIMx == TIM8)
224 {
225 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
226 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
227 }
228#endif /* TIM8 */
229#if defined(TIM9)
230 else if (TIMx == TIM9)
231 {
232 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
233 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
234 }
235#endif /* TIM9 */
236#if defined(TIM10)
237 else if (TIMx == TIM10)
238 {
239 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
240 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
241 }
242#endif /* TIM10 */
243#if defined(TIM11)
244 else if (TIMx == TIM11)
245 {
246 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
247 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
248 }
249#endif /* TIM11 */
250#if defined(TIM12)
251 else if (TIMx == TIM12)
252 {
253 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
254 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
255 }
256#endif /* TIM12 */
257#if defined(TIM13)
258 else if (TIMx == TIM13)
259 {
260 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
261 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
262 }
263#endif /* TIM13 */
264#if defined(TIM14)
265 else if (TIMx == TIM14)
266 {
267 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
268 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
269 }
270#endif /* TIM14 */
271 else
272 {
273 result = ERROR;
274 }
275
276 return result;
277}
278
285void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
286{
287 /* Set the default configuration */
288 TIM_InitStruct->Prescaler = (uint16_t)0x0000;
289 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
290 TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
291 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
292 TIM_InitStruct->RepetitionCounter = 0x00000000U;
293}
294
304ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)
305{
306 uint32_t tmpcr1;
307
308 /* Check the parameters */
309 assert_param(IS_TIM_INSTANCE(TIMx));
310 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
311 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
312
313 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
314
315 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
316 {
317 /* Select the Counter Mode */
318 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
319 }
320
321 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
322 {
323 /* Set the clock division */
324 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
325 }
326
327 /* Write to TIMx CR1 */
328 LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
329
330 /* Set the Autoreload value */
331 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
332
333 /* Set the Prescaler value */
334 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
335
336 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
337 {
338 /* Set the Repetition Counter value */
339 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
340 }
341
342 /* Generate an update event to reload the Prescaler
343 and the repetition counter value (if applicable) immediately */
344 LL_TIM_GenerateEvent_UPDATE(TIMx);
345
346 return SUCCESS;
347}
348
356void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
357{
358 /* Set the default configuration */
359 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
360 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
361 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
362 TIM_OC_InitStruct->CompareValue = 0x00000000U;
363 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
364 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
365 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
366 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
367}
368
383ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
384{
385 ErrorStatus result = ERROR;
386
387 switch (Channel)
388 {
389 case LL_TIM_CHANNEL_CH1:
390 result = OC1Config(TIMx, TIM_OC_InitStruct);
391 break;
392 case LL_TIM_CHANNEL_CH2:
393 result = OC2Config(TIMx, TIM_OC_InitStruct);
394 break;
395 case LL_TIM_CHANNEL_CH3:
396 result = OC3Config(TIMx, TIM_OC_InitStruct);
397 break;
398 case LL_TIM_CHANNEL_CH4:
399 result = OC4Config(TIMx, TIM_OC_InitStruct);
400 break;
401 default:
402 break;
403 }
404
405 return result;
406}
407
415void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
416{
417 /* Set the default configuration */
418 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
419 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
420 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
421 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
422}
423
438ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
439{
440 ErrorStatus result = ERROR;
441
442 switch (Channel)
443 {
444 case LL_TIM_CHANNEL_CH1:
445 result = IC1Config(TIMx, TIM_IC_InitStruct);
446 break;
447 case LL_TIM_CHANNEL_CH2:
448 result = IC2Config(TIMx, TIM_IC_InitStruct);
449 break;
450 case LL_TIM_CHANNEL_CH3:
451 result = IC3Config(TIMx, TIM_IC_InitStruct);
452 break;
453 case LL_TIM_CHANNEL_CH4:
454 result = IC4Config(TIMx, TIM_IC_InitStruct);
455 break;
456 default:
457 break;
458 }
459
460 return result;
461}
462
469void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
470{
471 /* Set the default configuration */
472 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
473 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
474 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
475 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
476 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
477 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
478 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
479 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
480 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
481}
482
492ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
493{
494 uint32_t tmpccmr1;
495 uint32_t tmpccer;
496
497 /* Check the parameters */
498 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
499 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
500 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
501 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
502 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
503 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
504 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
505 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
506 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
507 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
508
509 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
510 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
511
512 /* Get the TIMx CCMR1 register value */
513 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
514
515 /* Get the TIMx CCER register value */
516 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
517
518 /* Configure TI1 */
519 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
520 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
521 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
522 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
523
524 /* Configure TI2 */
525 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
526 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
527 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
528 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
529
530 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
531 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
532 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
533 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
534 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
535
536 /* Set encoder mode */
537 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
538
539 /* Write to TIMx CCMR1 */
540 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
541
542 /* Write to TIMx CCER */
543 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
544
545 return SUCCESS;
546}
547
555void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
556{
557 /* Set the default configuration */
558 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
559 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
560 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
561 TIM_HallSensorInitStruct->CommutationDelay = 0U;
562}
563
585ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
586{
587 uint32_t tmpcr2;
588 uint32_t tmpccmr1;
589 uint32_t tmpccer;
590 uint32_t tmpsmcr;
591
592 /* Check the parameters */
593 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
594 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
595 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
596 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
597
598 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
599 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
600
601 /* Get the TIMx CR2 register value */
602 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
603
604 /* Get the TIMx CCMR1 register value */
605 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
606
607 /* Get the TIMx CCER register value */
608 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
609
610 /* Get the TIMx SMCR register value */
611 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
612
613 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
614 tmpcr2 |= TIM_CR2_TI1S;
615
616 /* OC2REF signal is used as trigger output (TRGO) */
617 tmpcr2 |= LL_TIM_TRGO_OC2REF;
618
619 /* Configure the slave mode controller */
620 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
621 tmpsmcr |= LL_TIM_TS_TI1F_ED;
622 tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
623
624 /* Configure input channel 1 */
625 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
626 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
627 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
628 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
629
630 /* Configure input channel 2 */
631 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
632 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
633
634 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
635 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
636 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
637 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
638
639 /* Write to TIMx CR2 */
640 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
641
642 /* Write to TIMx SMCR */
643 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
644
645 /* Write to TIMx CCMR1 */
646 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
647
648 /* Write to TIMx CCER */
649 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
650
651 /* Write to TIMx CCR2 */
652 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
653
654 return SUCCESS;
655}
656
664void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
665{
666 /* Set the default configuration */
667 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
668 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
669 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
670 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
671 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
672 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
673 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
674}
675
690ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
691{
692 uint32_t tmpbdtr = 0;
693
694 /* Check the parameters */
695 assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
696 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
697 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
698 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
699 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
700 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
701 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
702
703 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
704 the OSSI State, the dead time value and the Automatic Output Enable Bit */
705
706 /* Set the BDTR bits */
707 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
708 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
709 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
710 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
711 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
712 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
713 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
714
715 /* Set TIMx_BDTR */
716 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
717
718 return SUCCESS;
719}
723
727
740static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
741{
742 uint32_t tmpccmr1;
743 uint32_t tmpccer;
744 uint32_t tmpcr2;
745
746 /* Check the parameters */
747 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
748 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
749 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
750 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
751
752 /* Disable the Channel 1: Reset the CC1E Bit */
753 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
754
755 /* Get the TIMx CCER register value */
756 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
757
758 /* Get the TIMx CR2 register value */
759 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
760
761 /* Get the TIMx CCMR1 register value */
762 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
763
764 /* Reset Capture/Compare selection Bits */
765 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
766
767 /* Set the Output Compare Mode */
768 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
769
770 /* Set the Output Compare Polarity */
771 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
772
773 /* Set the Output State */
774 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
775
776 if (IS_TIM_BREAK_INSTANCE(TIMx))
777 {
778 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
779 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
780 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
781 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
782
783 /* Set the complementary output Polarity */
784 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
785
786 /* Set the complementary output State */
787 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
788
789 /* Set the Output Idle state */
790 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
791
792 /* Set the complementary output Idle state */
793 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
794 }
795
796 /* Write to TIMx CR2 */
797 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
798
799 /* Write to TIMx CCMR1 */
800 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
801
802 /* Set the Capture Compare Register value */
803 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
804
805 /* Write to TIMx CCER */
806 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
807
808 return SUCCESS;
809}
810
819static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
820{
821 uint32_t tmpccmr1;
822 uint32_t tmpccer;
823 uint32_t tmpcr2;
824
825 /* Check the parameters */
826 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
827 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
828 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
829 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
830
831 /* Disable the Channel 2: Reset the CC2E Bit */
832 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
833
834 /* Get the TIMx CCER register value */
835 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
836
837 /* Get the TIMx CR2 register value */
838 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
839
840 /* Get the TIMx CCMR1 register value */
841 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
842
843 /* Reset Capture/Compare selection Bits */
844 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
845
846 /* Select the Output Compare Mode */
847 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
848
849 /* Set the Output Compare Polarity */
850 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
851
852 /* Set the Output State */
853 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
854
855 if (IS_TIM_BREAK_INSTANCE(TIMx))
856 {
857 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
858 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
859 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
860 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
861
862 /* Set the complementary output Polarity */
863 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
864
865 /* Set the complementary output State */
866 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
867
868 /* Set the Output Idle state */
869 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
870
871 /* Set the complementary output Idle state */
872 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
873 }
874
875 /* Write to TIMx CR2 */
876 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
877
878 /* Write to TIMx CCMR1 */
879 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
880
881 /* Set the Capture Compare Register value */
882 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
883
884 /* Write to TIMx CCER */
885 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
886
887 return SUCCESS;
888}
889
898static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
899{
900 uint32_t tmpccmr2;
901 uint32_t tmpccer;
902 uint32_t tmpcr2;
903
904 /* Check the parameters */
905 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
906 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
907 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
908 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
909
910 /* Disable the Channel 3: Reset the CC3E Bit */
911 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
912
913 /* Get the TIMx CCER register value */
914 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
915
916 /* Get the TIMx CR2 register value */
917 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
918
919 /* Get the TIMx CCMR2 register value */
920 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
921
922 /* Reset Capture/Compare selection Bits */
923 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
924
925 /* Select the Output Compare Mode */
926 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
927
928 /* Set the Output Compare Polarity */
929 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
930
931 /* Set the Output State */
932 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
933
934 if (IS_TIM_BREAK_INSTANCE(TIMx))
935 {
936 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
937 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
938 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
939 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
940
941 /* Set the complementary output Polarity */
942 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
943
944 /* Set the complementary output State */
945 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
946
947 /* Set the Output Idle state */
948 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
949
950 /* Set the complementary output Idle state */
951 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
952 }
953
954 /* Write to TIMx CR2 */
955 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
956
957 /* Write to TIMx CCMR2 */
958 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
959
960 /* Set the Capture Compare Register value */
961 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
962
963 /* Write to TIMx CCER */
964 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
965
966 return SUCCESS;
967}
968
977static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
978{
979 uint32_t tmpccmr2;
980 uint32_t tmpccer;
981 uint32_t tmpcr2;
982
983 /* Check the parameters */
984 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
985 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
986 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
987 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
988
989 /* Disable the Channel 4: Reset the CC4E Bit */
990 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
991
992 /* Get the TIMx CCER register value */
993 tmpccer = LL_TIM_ReadReg(TIMx, CCER);
994
995 /* Get the TIMx CR2 register value */
996 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
997
998 /* Get the TIMx CCMR2 register value */
999 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1000
1001 /* Reset Capture/Compare selection Bits */
1002 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1003
1004 /* Select the Output Compare Mode */
1005 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1006
1007 /* Set the Output Compare Polarity */
1008 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1009
1010 /* Set the Output State */
1011 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1012
1013 if (IS_TIM_BREAK_INSTANCE(TIMx))
1014 {
1015 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1016
1017 /* Set the Output Idle state */
1018 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1019 }
1020
1021 /* Write to TIMx CR2 */
1022 LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1023
1024 /* Write to TIMx CCMR2 */
1025 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1026
1027 /* Set the Capture Compare Register value */
1028 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1029
1030 /* Write to TIMx CCER */
1031 LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1032
1033 return SUCCESS;
1034}
1035
1044static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1045{
1046 /* Check the parameters */
1047 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1048 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1049 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1050 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1051 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1052
1053 /* Disable the Channel 1: Reset the CC1E Bit */
1054 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1055
1056 /* Select the Input and set the filter and the prescaler value */
1057 MODIFY_REG(TIMx->CCMR1,
1058 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1059 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1060
1061 /* Select the Polarity and set the CC1E Bit */
1062 MODIFY_REG(TIMx->CCER,
1063 (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1064 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1065
1066 return SUCCESS;
1067}
1068
1077static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1078{
1079 /* Check the parameters */
1080 assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1081 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1082 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1083 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1084 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1085
1086 /* Disable the Channel 2: Reset the CC2E Bit */
1087 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1088
1089 /* Select the Input and set the filter and the prescaler value */
1090 MODIFY_REG(TIMx->CCMR1,
1091 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1092 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1093
1094 /* Select the Polarity and set the CC2E Bit */
1095 MODIFY_REG(TIMx->CCER,
1096 (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1097 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1098
1099 return SUCCESS;
1100}
1101
1110static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1111{
1112 /* Check the parameters */
1113 assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1114 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1115 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1116 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1117 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1118
1119 /* Disable the Channel 3: Reset the CC3E Bit */
1120 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1121
1122 /* Select the Input and set the filter and the prescaler value */
1123 MODIFY_REG(TIMx->CCMR2,
1124 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1125 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1126
1127 /* Select the Polarity and set the CC3E Bit */
1128 MODIFY_REG(TIMx->CCER,
1129 (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1130 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1131
1132 return SUCCESS;
1133}
1134
1143static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1144{
1145 /* Check the parameters */
1146 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1147 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1148 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1149 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1150 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1151
1152 /* Disable the Channel 4: Reset the CC4E Bit */
1153 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1154
1155 /* Select the Input and set the filter and the prescaler value */
1156 MODIFY_REG(TIMx->CCMR2,
1157 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1158 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1159
1160 /* Select the Polarity and set the CC4E Bit */
1161 MODIFY_REG(TIMx->CCER,
1162 (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1163 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1164
1165 return SUCCESS;
1166}
1167
1168
1172
1176
1177#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */
1178
1182
1183#endif /* USE_FULL_LL_DRIVER */
1184
assert_param
#define assert_param(expr)
Definition stm32_assert_template.h:46
stm32f4xx_ll_bus.h
Header file of BUS LL module.
stm32f4xx_ll_tim.h
Header file of TIM LL module.