STM32F4xx HAL Driver master
STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_ll_system.h
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1
32
33/* Define to prevent recursive inclusion -------------------------------------*/
34#ifndef __STM32F4xx_LL_SYSTEM_H
35#define __STM32F4xx_LL_SYSTEM_H
36
37#ifdef __cplusplus
38extern "C" {
39#endif
40
41/* Includes ------------------------------------------------------------------*/
42#include "stm32f4xx.h"
43
47
48#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
49
53
54/* Private types -------------------------------------------------------------*/
55/* Private variables ---------------------------------------------------------*/
56
57/* Private constants ---------------------------------------------------------*/
61
65
66/* Private macros ------------------------------------------------------------*/
67
68/* Exported types ------------------------------------------------------------*/
69/* Exported constants --------------------------------------------------------*/
73
77#define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000
78#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0
79#if defined(FSMC_Bank1)
80#define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1
81#endif /* FSMC_Bank1 */
82#if defined(FMC_Bank1)
83#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1
84#define LL_SYSCFG_REMAP_SDRAM SYSCFG_MEMRMP_MEM_MODE_2
85#endif /* FMC_Bank1 */
86#define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0)
87
91
92#if defined(SYSCFG_PMC_MII_RMII_SEL)
96#define LL_SYSCFG_PMC_ETHMII (uint32_t)0x00000000
97#define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL
98
102#endif /* SYSCFG_PMC_MII_RMII_SEL */
103
104
105
106#if defined(SYSCFG_MEMRMP_UFB_MODE)
110#define LL_SYSCFG_BANKMODE_BANK1 (uint32_t)0x00000000
112#define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_UFB_MODE
117#endif /* SYSCFG_MEMRMP_UFB_MODE */
121#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
122#define LL_SYSCFG_I2C_FASTMODEPLUS_SCL SYSCFG_CFGR_FMPI2C1_SCL
123#define LL_SYSCFG_I2C_FASTMODEPLUS_SDA SYSCFG_CFGR_FMPI2C1_SDA
124#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
128
132#define LL_SYSCFG_EXTI_PORTA (uint32_t)0
133#define LL_SYSCFG_EXTI_PORTB (uint32_t)1
134#define LL_SYSCFG_EXTI_PORTC (uint32_t)2
135#define LL_SYSCFG_EXTI_PORTD (uint32_t)3
136#define LL_SYSCFG_EXTI_PORTE (uint32_t)4
137#if defined(GPIOF)
138#define LL_SYSCFG_EXTI_PORTF (uint32_t)5
139#endif /* GPIOF */
140#if defined(GPIOG)
141#define LL_SYSCFG_EXTI_PORTG (uint32_t)6
142#endif /* GPIOG */
143#define LL_SYSCFG_EXTI_PORTH (uint32_t)7
144#if defined(GPIOI)
145#define LL_SYSCFG_EXTI_PORTI (uint32_t)8
146#endif /* GPIOI */
147#if defined(GPIOJ)
148#define LL_SYSCFG_EXTI_PORTJ (uint32_t)9
149#endif /* GPIOJ */
150#if defined(GPIOK)
151#define LL_SYSCFG_EXTI_PORTK (uint32_t)10
152#endif /* GPIOK */
156
160#define LL_SYSCFG_EXTI_LINE0 (uint32_t)(0x000FU << 16 | 0)
161#define LL_SYSCFG_EXTI_LINE1 (uint32_t)(0x00F0U << 16 | 0)
162#define LL_SYSCFG_EXTI_LINE2 (uint32_t)(0x0F00U << 16 | 0)
163#define LL_SYSCFG_EXTI_LINE3 (uint32_t)(0xF000U << 16 | 0)
164#define LL_SYSCFG_EXTI_LINE4 (uint32_t)(0x000FU << 16 | 1)
165#define LL_SYSCFG_EXTI_LINE5 (uint32_t)(0x00F0U << 16 | 1)
166#define LL_SYSCFG_EXTI_LINE6 (uint32_t)(0x0F00U << 16 | 1)
167#define LL_SYSCFG_EXTI_LINE7 (uint32_t)(0xF000U << 16 | 1)
168#define LL_SYSCFG_EXTI_LINE8 (uint32_t)(0x000FU << 16 | 2)
169#define LL_SYSCFG_EXTI_LINE9 (uint32_t)(0x00F0U << 16 | 2)
170#define LL_SYSCFG_EXTI_LINE10 (uint32_t)(0x0F00U << 16 | 2)
171#define LL_SYSCFG_EXTI_LINE11 (uint32_t)(0xF000U << 16 | 2)
172#define LL_SYSCFG_EXTI_LINE12 (uint32_t)(0x000FU << 16 | 3)
173#define LL_SYSCFG_EXTI_LINE13 (uint32_t)(0x00F0U << 16 | 3)
174#define LL_SYSCFG_EXTI_LINE14 (uint32_t)(0x0F00U << 16 | 3)
175#define LL_SYSCFG_EXTI_LINE15 (uint32_t)(0xF000U << 16 | 3)
179
183#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
184#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_LOCKUP_LOCK
186#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVD_LOCK
188#endif /* SYSCFG_CFGR2_CLL */
192
193#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
197#define LL_SYSCFG_BITSTREAM_CLOCK_TIM2OC1 (uint32_t)0x00000000
198#define LL_SYSCFG_BITSTREAM_CLOCK_DFSDM2 SYSCFG_MCHDLYCR_BSCKSEL
205#define LL_SYSCFG_DFSDM1_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY1EN
206#define LL_SYSCFG_DFSDM2_MCHDLYEN SYSCFG_MCHDLYCR_MCHDLY2EN
213#define LL_SYSCFG_DFSDM1_DataIn0 SYSCFG_MCHDLYCR_DFSDM1D0SEL
214#define LL_SYSCFG_DFSDM2_DataIn0 SYSCFG_MCHDLYCR_DFSDM2D0SEL
215
216#define LL_SYSCFG_DFSDM1_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | 0x00000000)
217#define LL_SYSCFG_DFSDM1_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D0SEL)
218#define LL_SYSCFG_DFSDM2_DataIn0_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | 0x00000000)
219#define LL_SYSCFG_DFSDM2_DataIn0_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D0SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D0SEL)
226#define LL_SYSCFG_DFSDM1_DataIn2 SYSCFG_MCHDLYCR_DFSDM1D2SEL
227#define LL_SYSCFG_DFSDM2_DataIn2 SYSCFG_MCHDLYCR_DFSDM2D2SEL
228
229#define LL_SYSCFG_DFSDM1_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | 0x00000000)
230#define LL_SYSCFG_DFSDM1_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM1D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM1D2SEL)
231#define LL_SYSCFG_DFSDM2_DataIn2_PAD (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | 0x00000000)
232#define LL_SYSCFG_DFSDM2_DataIn2_DM (uint32_t)((SYSCFG_MCHDLYCR_DFSDM2D2SEL << 16) | SYSCFG_MCHDLYCR_DFSDM2D2SEL)
239#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN0 (uint32_t)0x00000000
240#define LL_SYSCFG_DFSDM1_TIM4OC2_CLKIN2 SYSCFG_MCHDLYCR_DFSDM1CK02SEL
247#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN1 (uint32_t)0x00000000
248#define LL_SYSCFG_DFSDM1_TIM4OC1_CLKIN3 SYSCFG_MCHDLYCR_DFSDM1CK13SEL
255#define LL_SYSCFG_DFSDM1_CKIN_PAD (uint32_t)0x00000000
256#define LL_SYSCFG_DFSDM1_CKIN_DM SYSCFG_MCHDLYCR_DFSDM1CFG
263#define LL_SYSCFG_DFSDM1_CKOUT (uint32_t)0x00000000
264#define LL_SYSCFG_DFSDM1_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM1CKOSEL
268
272#define LL_SYSCFG_DFSDM2_DataIn4_PAD (uint32_t)0x00000000
273#define LL_SYSCFG_DFSDM2_DataIn4_DM SYSCFG_MCHDLYCR_DFSDM2D4SEL
280#define LL_SYSCFG_DFSDM2_DataIn6_PAD (uint32_t)0x00000000
281#define LL_SYSCFG_DFSDM2_DataIn6_DM SYSCFG_MCHDLYCR_DFSDM2D6SEL
288#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN0 (uint32_t)0x00000000
289#define LL_SYSCFG_DFSDM2_TIM3OC4_CLKIN4 SYSCFG_MCHDLYCR_DFSDM2CK04SEL
296#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN1 (uint32_t)0x00000000
297#define LL_SYSCFG_DFSDM2_TIM3OC3_CLKIN5 SYSCFG_MCHDLYCR_DFSDM2CK15SEL
304#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN2 (uint32_t)0x00000000
305#define LL_SYSCFG_DFSDM2_TIM3OC2_CLKIN6 SYSCFG_MCHDLYCR_DFSDM2CK26SEL
312#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN3 (uint32_t)0x00000000
313#define LL_SYSCFG_DFSDM2_TIM3OC1_CLKIN7 SYSCFG_MCHDLYCR_DFSDM2CK37SEL
320#define LL_SYSCFG_DFSDM2_CKIN_PAD (uint32_t)0x00000000
321#define LL_SYSCFG_DFSDM2_CKIN_DM SYSCFG_MCHDLYCR_DFSDM2CFG
328#define LL_SYSCFG_DFSDM2_CKOUT (uint32_t)0x00000000
329#define LL_SYSCFG_DFSDM2_CKOUT_M27 SYSCFG_MCHDLYCR_DFSDM2CKOSEL
333#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
334
338#define LL_DBGMCU_TRACE_NONE 0x00000000U
339#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN
340#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0)
341#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1)
342#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)
346
350#if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
351#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP
352#endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
353#if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
354#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP
355#endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
356#if defined(DBGMCU_APB1_FZ_DBG_TIM4_STOP)
357#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP
358#endif /* DBGMCU_APB1_FZ_DBG_TIM4_STOP */
359#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP
360#if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
361#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP
362#endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
363#if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
364#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP
365#endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
366#if defined(DBGMCU_APB1_FZ_DBG_TIM12_STOP)
367#define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP
368#endif /* DBGMCU_APB1_FZ_DBG_TIM12_STOP */
369#if defined(DBGMCU_APB1_FZ_DBG_TIM13_STOP)
370#define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP
371#endif /* DBGMCU_APB1_FZ_DBG_TIM13_STOP */
372#if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
373#define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP
374#endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
375#if defined(DBGMCU_APB1_FZ_DBG_LPTIM_STOP)
376#define LL_DBGMCU_APB1_GRP1_LPTIM_STOP DBGMCU_APB1_FZ_DBG_LPTIM_STOP
377#endif /* DBGMCU_APB1_FZ_DBG_LPTIM_STOP */
378#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP
379#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP
380#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
381#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT
382#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT
383#if defined(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT)
384#define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT
385#endif /* DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT */
386#if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
387#define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT
388#endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
389#if defined(DBGMCU_APB1_FZ_DBG_CAN1_STOP)
390#define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP
391#endif /* DBGMCU_APB1_FZ_DBG_CAN1_STOP */
392#if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
393#define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP
394#endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
395#if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
396#define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP
397#endif /* DBGMCU_APB1_FZ_DBG_CAN3_STOP */
401
405#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP
406#if defined(DBGMCU_APB2_FZ_DBG_TIM8_STOP)
407#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP
408#endif /* DBGMCU_APB2_FZ_DBG_TIM8_STOP */
409#define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP
410#if defined(DBGMCU_APB2_FZ_DBG_TIM10_STOP)
411#define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP
412#endif /* DBGMCU_APB2_FZ_DBG_TIM10_STOP */
413#define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP
417
421#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS
422#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS
423#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS
424#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS
425#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS
426#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS
427#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS
428#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS
429#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS
430#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS
431#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS
432#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS
433#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS
434#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS
435#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS
436#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS
440
444
445/* Exported macro ------------------------------------------------------------*/
446
447/* Exported functions --------------------------------------------------------*/
451
466__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory)
467{
468 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, Memory);
469}
470
481__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void)
482{
483 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE));
484}
485
486#if defined(SYSCFG_MEMRMP_SWP_FMC)
494__STATIC_INLINE void LL_SYSCFG_EnableFMCMemorySwapping(void)
495{
496 SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC_0);
497}
498
506__STATIC_INLINE void LL_SYSCFG_DisableFMCMemorySwapping(void)
507{
508 CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FMC);
509}
510
511#endif /* SYSCFG_MEMRMP_SWP_FMC */
519__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)
520{
521 SET_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
522}
523
531__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)
532{
533 CLEAR_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_CMP_PD);
534}
535
541__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
542{
543 return (READ_BIT(SYSCFG->CMPCR, SYSCFG_CMPCR_READY) == (SYSCFG_CMPCR_READY));
544}
545
546#if defined(SYSCFG_PMC_MII_RMII_SEL)
555__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)
556{
557 MODIFY_REG(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL, Interface);
558}
559
568__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)
569{
570 return (uint32_t)(READ_BIT(SYSCFG->PMC, SYSCFG_PMC_MII_RMII_SEL));
571}
572#endif /* SYSCFG_PMC_MII_RMII_SEL */
573
574
575
576#if defined(SYSCFG_MEMRMP_UFB_MODE)
585__STATIC_INLINE void LL_SYSCFG_SetFlashBankMode(uint32_t Bank)
586{
587 MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE, Bank);
588}
589
597__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashBankMode(void)
598{
599 return (uint32_t)(READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_UFB_MODE));
600}
601#endif /* SYSCFG_MEMRMP_UFB_MODE */
602
603#if defined(SYSCFG_CFGR_FMPI2C1_SCL)
614__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)
615{
616 SET_BIT(SYSCFG->CFGR, ConfigFastModePlus);
617}
618
629__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)
630{
631 CLEAR_BIT(SYSCFG->CFGR, ConfigFastModePlus);
632}
633#endif /* SYSCFG_CFGR_FMPI2C1_SCL */
634
671__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)
672{
673 MODIFY_REG(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16)));
674}
675
710__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)
711{
712 return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16));
713}
714
715#if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
725__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)
726{
727 MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK, Break);
728}
729
738__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
739{
740 return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_LOCKUP_LOCK | SYSCFG_CFGR2_PVD_LOCK));
741}
742#endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
743#if defined(SYSCFG_MCHDLYCR_BSCKSEL)
752__STATIC_INLINE void LL_SYSCFG_DFSDM_SetBitstreamClockSourceSelection(uint32_t ClockSource)
753{
754 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL, ClockSource);
755}
764__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetBitstreamClockSourceSelection(void)
765{
766 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_BSCKSEL));
767}
776__STATIC_INLINE void LL_SYSCFG_DFSDM_EnableDelayClock(uint32_t MCHDLY)
777{
778 SET_BIT(SYSCFG->MCHDLYCR, MCHDLY);
779}
780
789__STATIC_INLINE void LL_SYSCFG_DFSDM_DisableDelayClock(uint32_t MCHDLY)
790{
791 CLEAR_BIT(SYSCFG->MCHDLYCR, MCHDLY);
792}
793
804__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn0Source(uint32_t Source)
805{
806 MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
807}
821__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn0Source(uint32_t Source)
822{
823 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
824}
835__STATIC_INLINE void LL_SYSCFG_DFSDM_SetDataIn2Source(uint32_t Source)
836{
837 MODIFY_REG(SYSCFG->MCHDLYCR, (Source >> 16), (Source & 0x0000FFFF));
838}
852__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM_GetDataIn2Source(uint32_t Source)
853{
854 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, Source));
855}
856
865__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC2BitStreamDistribution(uint32_t Source)
866{
867 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL, Source);
868}
877__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC2BitStreamDistribution(void)
878{
879 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK02SEL));
880}
881
890__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetTIM4OC1BitStreamDistribution(uint32_t Source)
891{
892 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL, Source);
893}
902__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetTIM4OC1BitStreamDistribution(void)
903{
904 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CK13SEL));
905}
906
915__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockInSourceSelection(uint32_t ClockSource)
916{
917 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG, ClockSource);
918}
927__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockInSourceSelection(void)
928{
929 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CFG));
930}
931
940__STATIC_INLINE void LL_SYSCFG_DFSDM1_SetClockOutSourceSelection(uint32_t ClockSource)
941{
942 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL, ClockSource);
943}
952__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM1_GetClockOutSourceSelection(void)
953{
954 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM1CKOSEL));
955}
956
962__STATIC_INLINE void LL_SYSCFG_DFSDM2_EnableDelayClock(void)
963{
964 SET_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
965}
966
972__STATIC_INLINE void LL_SYSCFG_DFSDM2_DisableDelayClock(void)
973{
974 CLEAR_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_MCHDLY2EN);
975}
984__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn0Source(uint32_t Source)
985{
986 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL, Source);
987}
996__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn0Source(void)
997{
998 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D0SEL));
999}
1000
1009__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn2Source(uint32_t Source)
1010{
1011 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL, Source);
1012}
1021__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn2Source(void)
1022{
1023 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D2SEL));
1024}
1025
1034__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn4Source(uint32_t Source)
1035{
1036 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL, Source);
1037}
1046__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn4Source(void)
1047{
1048 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D4SEL));
1049}
1050
1059__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetDataIn6Source(uint32_t Source)
1060{
1061 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL, Source);
1062}
1071__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetDataIn6Source(void)
1072{
1073 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2D6SEL));
1074}
1075
1084__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC4BitStreamDistribution(uint32_t Source)
1085{
1086 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL, Source);
1087}
1096__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC4BitStreamDistribution(void)
1097{
1098 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK04SEL));
1099}
1100
1109__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC3BitStreamDistribution(uint32_t Source)
1110{
1111 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL, Source);
1112}
1121__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC3BitStreamDistribution(void)
1122{
1123 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK15SEL));
1124}
1125
1134__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC2BitStreamDistribution(uint32_t Source)
1135{
1136 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL, Source);
1137}
1146__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC2BitStreamDistribution(void)
1147{
1148 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK26SEL));
1149}
1150
1159__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetTIM3OC1BitStreamDistribution(uint32_t Source)
1160{
1161 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL, Source);
1162}
1171__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetTIM3OC1BitStreamDistribution(void)
1172{
1173 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CK37SEL));
1174}
1175
1184__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockInSourceSelection(uint32_t ClockSource)
1185{
1186 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG, ClockSource);
1187}
1196__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockInSourceSelection(void)
1197{
1198 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CFG));
1199}
1200
1209__STATIC_INLINE void LL_SYSCFG_DFSDM2_SetClockOutSourceSelection(uint32_t ClockSource)
1210{
1211 MODIFY_REG(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL, ClockSource);
1212}
1221__STATIC_INLINE uint32_t LL_SYSCFG_DFSDM2_GetClockOutSourceSelection(void)
1222{
1223 return (uint32_t)(READ_BIT(SYSCFG->MCHDLYCR, SYSCFG_MCHDLYCR_DFSDM2CKOSEL));
1224}
1225
1226#endif /* SYSCFG_MCHDLYCR_BSCKSEL */
1230
1231
1235
1251__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)
1252{
1253 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));
1254}
1255
1268__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)
1269{
1270 return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);
1271}
1272
1278__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void)
1279{
1280 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1281}
1282
1288__STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void)
1289{
1290 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
1291}
1292
1298__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void)
1299{
1300 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1301}
1302
1308__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void)
1309{
1310 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
1311}
1312
1318__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void)
1319{
1320 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1321}
1322
1328__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void)
1329{
1330 CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
1331}
1332
1345__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment)
1346{
1347 MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment);
1348}
1349
1361__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void)
1362{
1363 return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE));
1364}
1365
1413__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)
1414{
1415 SET_BIT(DBGMCU->APB1FZ, Periphs);
1416}
1417
1465__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)
1466{
1467 CLEAR_BIT(DBGMCU->APB1FZ, Periphs);
1468}
1469
1487__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)
1488{
1489 SET_BIT(DBGMCU->APB2FZ, Periphs);
1490}
1491
1509__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)
1510{
1511 CLEAR_BIT(DBGMCU->APB2FZ, Periphs);
1512}
1516
1520
1543__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)
1544{
1545 MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);
1546}
1547
1569__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)
1570{
1571 return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));
1572}
1573
1579__STATIC_INLINE void LL_FLASH_EnablePrefetch(void)
1580{
1581 SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1582}
1583
1589__STATIC_INLINE void LL_FLASH_DisablePrefetch(void)
1590{
1591 CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN);
1592}
1593
1599__STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void)
1600{
1601 return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) == (FLASH_ACR_PRFTEN));
1602}
1603
1609__STATIC_INLINE void LL_FLASH_EnableInstCache(void)
1610{
1611 SET_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1612}
1613
1619__STATIC_INLINE void LL_FLASH_DisableInstCache(void)
1620{
1621 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICEN);
1622}
1623
1629__STATIC_INLINE void LL_FLASH_EnableDataCache(void)
1630{
1631 SET_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1632}
1633
1639__STATIC_INLINE void LL_FLASH_DisableDataCache(void)
1640{
1641 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCEN);
1642}
1643
1650__STATIC_INLINE void LL_FLASH_EnableInstCacheReset(void)
1651{
1652 SET_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1653}
1654
1660__STATIC_INLINE void LL_FLASH_DisableInstCacheReset(void)
1661{
1662 CLEAR_BIT(FLASH->ACR, FLASH_ACR_ICRST);
1663}
1664
1671__STATIC_INLINE void LL_FLASH_EnableDataCacheReset(void)
1672{
1673 SET_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1674}
1675
1681__STATIC_INLINE void LL_FLASH_DisableDataCacheReset(void)
1682{
1683 CLEAR_BIT(FLASH->ACR, FLASH_ACR_DCRST);
1684}
1685
1686
1690
1694
1698
1699#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
1700
1704
1705#ifdef __cplusplus
1706}
1707#endif
1708
1709#endif /* __STM32F4xx_LL_SYSTEM_H */
1710
1711