STM32F4xx HAL Driver master
STM32CubeF4 HAL / LL Drivers API Reference
Loading...
Searching...
No Matches
stm32f4xx_ll_spi.h
Go to the documentation of this file.
1
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32F4xx_LL_SPI_H
21#define STM32F4xx_LL_SPI_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f4xx.h"
29
33
34#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
35
39
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42/* Private macros ------------------------------------------------------------*/
43
44/* Exported types ------------------------------------------------------------*/
45#if defined(USE_FULL_LL_DRIVER)
49
53typedef struct
54{
55 uint32_t TransferDirection;
60
61 uint32_t Mode;
66
67 uint32_t DataWidth;
72
73 uint32_t ClockPolarity;
78
79 uint32_t ClockPhase;
84
85 uint32_t NSS;
91
92 uint32_t BaudRate;
100
101 uint32_t BitOrder;
106
107 uint32_t CRCCalculation;
112
113 uint32_t CRCPoly;
118
119} LL_SPI_InitTypeDef;
120
124#endif /* USE_FULL_LL_DRIVER */
125
126/* Exported constants --------------------------------------------------------*/
130
135#define LL_SPI_SR_RXNE SPI_SR_RXNE
136#define LL_SPI_SR_TXE SPI_SR_TXE
137#define LL_SPI_SR_BSY SPI_SR_BSY
138#define LL_SPI_SR_CRCERR SPI_SR_CRCERR
139#define LL_SPI_SR_MODF SPI_SR_MODF
140#define LL_SPI_SR_OVR SPI_SR_OVR
141#define LL_SPI_SR_FRE SPI_SR_FRE
145
150#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE
151#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE
152#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE
156
160#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
161#define LL_SPI_MODE_SLAVE 0x00000000U
165
169#define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U
170#define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF)
174
178#define LL_SPI_PHASE_1EDGE 0x00000000U
179#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA)
183
187#define LL_SPI_POLARITY_LOW 0x00000000U
188#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL)
192
196#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U
197#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0)
198#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1)
199#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
200#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2)
201#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
202#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
203#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
207
211#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST)
212#define LL_SPI_MSB_FIRST 0x00000000U
216
220#define LL_SPI_FULL_DUPLEX 0x00000000U
221#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY)
222#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE)
223#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)
227
231#define LL_SPI_NSS_SOFT (SPI_CR1_SSM)
232#define LL_SPI_NSS_HARD_INPUT 0x00000000U
233#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U))
237
241#define LL_SPI_DATAWIDTH_8BIT 0x00000000U
242#define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF)
246#if defined(USE_FULL_LL_DRIVER)
247
251#define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U
252#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN)
256#endif /* USE_FULL_LL_DRIVER */
257
261
262/* Exported macro ------------------------------------------------------------*/
266
270
278#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
279
286#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
290
294
295/* Exported functions --------------------------------------------------------*/
299
303
310__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)
311{
312 SET_BIT(SPIx->CR1, SPI_CR1_SPE);
313}
314
322__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)
323{
324 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
325}
326
333__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx)
334{
335 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);
336}
337
349__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)
350{
351 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode);
352}
353
363__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx)
364{
365 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI));
366}
367
378__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
379{
380 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard);
381}
382
391__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx)
392{
393 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF));
394}
395
407__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)
408{
409 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase);
410}
411
420__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx)
421{
422 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA));
423}
424
436__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
437{
438 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity);
439}
440
449__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx)
450{
451 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL));
452}
453
470__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate)
471{
472 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate);
473}
474
489__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx)
490{
491 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR));
492}
493
504__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)
505{
506 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder);
507}
508
517__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx)
518{
519 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST));
520}
521
537__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)
538{
539 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection);
540}
541
554__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx)
555{
556 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE));
557}
558
568__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)
569{
570 MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth);
571}
572
581__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx)
582{
583 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF));
584}
585
589
593
601__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)
602{
603 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN);
604}
605
613__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)
614{
615 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN);
616}
617
625__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx)
626{
627 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL);
628}
629
637__STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx)
638{
639 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT);
640}
641
649__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)
650{
651 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly);
652}
653
660__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx)
661{
662 return (uint32_t)(READ_REG(SPIx->CRCPR));
663}
664
671__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx)
672{
673 return (uint32_t)(READ_REG(SPIx->RXCRCR));
674}
675
682__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx)
683{
684 return (uint32_t)(READ_REG(SPIx->TXCRCR));
685}
686
690
694
707__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)
708{
709 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS);
710 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U)));
711}
712
723__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx)
724{
725 uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
726 uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
727 return (Ssm | Ssoe);
728}
729
733
737
744__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx)
745{
746 return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL);
747}
748
755__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx)
756{
757 return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL);
758}
759
766__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx)
767{
768 return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL);
769}
770
777__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx)
778{
779 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);
780}
781
788__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
789{
790 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);
791}
792
806__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx)
807{
808 return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL);
809}
810
817__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
818{
819 return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL);
820}
821
828__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)
829{
830 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR);
831}
832
841__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)
842{
843 __IO uint32_t tmpreg_sr;
844 tmpreg_sr = SPIx->SR;
845 (void) tmpreg_sr;
846 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);
847}
848
857__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx)
858{
859 __IO uint32_t tmpreg;
860 tmpreg = SPIx->DR;
861 (void) tmpreg;
862 tmpreg = SPIx->SR;
863 (void) tmpreg;
864}
865
873__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx)
874{
875 __IO uint32_t tmpreg;
876 tmpreg = SPIx->SR;
877 (void) tmpreg;
878}
879
883
887
896__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx)
897{
898 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE);
899}
900
907__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx)
908{
909 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
910}
911
918__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx)
919{
920 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE);
921}
922
931__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx)
932{
933 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE);
934}
935
942__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx)
943{
944 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE);
945}
946
953__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx)
954{
955 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE);
956}
957
964__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx)
965{
966 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL);
967}
968
975__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx)
976{
977 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL);
978}
979
986__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx)
987{
988 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL);
989}
990
994
998
1005__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1006{
1007 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1008}
1009
1016__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1017{
1018 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN);
1019}
1020
1027__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
1028{
1029 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL);
1030}
1031
1038__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1039{
1040 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1041}
1042
1049__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1050{
1051 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN);
1052}
1053
1060__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
1061{
1062 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL);
1063}
1064
1071__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx)
1072{
1073 return (uint32_t) &(SPIx->DR);
1074}
1075
1079
1083
1090__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
1091{
1092 return (*((__IO uint8_t *)&SPIx->DR));
1093}
1094
1101__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)
1102{
1103 return (uint16_t)(READ_REG(SPIx->DR));
1104}
1105
1113__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)
1114{
1115#if defined (__GNUC__)
1116 __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR);
1117 *spidr = TxData;
1118#else
1119 *((__IO uint8_t *)&SPIx->DR) = TxData;
1120#endif /* __GNUC__ */
1121}
1122
1130__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1131{
1132#if defined (__GNUC__)
1133 __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR);
1134 *spidr = TxData;
1135#else
1136 SPIx->DR = TxData;
1137#endif /* __GNUC__ */
1138}
1139
1143#if defined(USE_FULL_LL_DRIVER)
1147
1148ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx);
1149ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);
1150void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);
1151
1155#endif /* USE_FULL_LL_DRIVER */
1159
1163
1167
1168/* Private variables ---------------------------------------------------------*/
1169/* Private constants ---------------------------------------------------------*/
1170/* Private macros ------------------------------------------------------------*/
1171
1172/* Exported types ------------------------------------------------------------*/
1173#if defined(USE_FULL_LL_DRIVER)
1177
1181
1182typedef struct
1183{
1184 uint32_t Mode;
1188
1189 uint32_t Standard;
1193
1194
1195 uint32_t DataFormat;
1199
1200
1201 uint32_t MCLKOutput;
1205
1206
1207 uint32_t AudioFreq;
1212
1213
1214 uint32_t ClockPolarity;
1218
1219} LL_I2S_InitTypeDef;
1220
1224#endif /*USE_FULL_LL_DRIVER*/
1225
1226/* Exported constants --------------------------------------------------------*/
1230
1235#define LL_I2S_SR_RXNE LL_SPI_SR_RXNE
1236#define LL_I2S_SR_TXE LL_SPI_SR_TXE
1237#define LL_I2S_SR_BSY LL_SPI_SR_BSY
1238#define LL_I2S_SR_UDR SPI_SR_UDR
1239#define LL_I2S_SR_OVR LL_SPI_SR_OVR
1240#define LL_I2S_SR_FRE LL_SPI_SR_FRE
1244
1249#define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE
1250#define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE
1251#define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE
1255
1259#define LL_I2S_DATAFORMAT_16B 0x00000000U
1260#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN)
1261#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)
1262#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)
1266
1270#define LL_I2S_POLARITY_LOW 0x00000000U
1271#define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL)
1275
1279#define LL_I2S_STANDARD_PHILIPS 0x00000000U
1280#define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0)
1281#define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1)
1282#define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)
1283#define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)
1287
1291#define LL_I2S_MODE_SLAVE_TX 0x00000000U
1292#define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0)
1293#define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1)
1294#define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)
1298
1302#define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U
1303#define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U)
1307
1308#if defined(USE_FULL_LL_DRIVER)
1309
1313#define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U
1314#define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE)
1318
1322
1323#define LL_I2S_AUDIOFREQ_192K 192000U
1324#define LL_I2S_AUDIOFREQ_96K 96000U
1325#define LL_I2S_AUDIOFREQ_48K 48000U
1326#define LL_I2S_AUDIOFREQ_44K 44100U
1327#define LL_I2S_AUDIOFREQ_32K 32000U
1328#define LL_I2S_AUDIOFREQ_22K 22050U
1329#define LL_I2S_AUDIOFREQ_16K 16000U
1330#define LL_I2S_AUDIOFREQ_11K 11025U
1331#define LL_I2S_AUDIOFREQ_8K 8000U
1332#define LL_I2S_AUDIOFREQ_DEFAULT 2U
1336#endif /* USE_FULL_LL_DRIVER */
1337
1341
1342/* Exported macro ------------------------------------------------------------*/
1346
1350
1358#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1359
1366#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1370
1374
1375
1376/* Exported functions --------------------------------------------------------*/
1377
1381
1385
1393__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)
1394{
1395 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1396}
1397
1404__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)
1405{
1406 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE);
1407}
1408
1415__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx)
1416{
1417 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL);
1418}
1419
1432__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat)
1433{
1434 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat);
1435}
1436
1448__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx)
1449{
1450 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN));
1451}
1452
1462__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)
1463{
1464 SET_BIT(SPIx->I2SCFGR, ClockPolarity);
1465}
1466
1475__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx)
1476{
1477 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));
1478}
1479
1493__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)
1494{
1495 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);
1496}
1497
1510__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx)
1511{
1512 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));
1513}
1514
1526__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode)
1527{
1528 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode);
1529}
1530
1541__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx)
1542{
1543 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));
1544}
1545
1553__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear)
1554{
1555 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear);
1556}
1557
1564__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx)
1565{
1566 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV));
1567}
1568
1578__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)
1579{
1580 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U);
1581}
1582
1591__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx)
1592{
1593 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
1594}
1595
1602__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
1603{
1604 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1605}
1606
1613__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
1614{
1615 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1616}
1617
1624__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx)
1625{
1626 return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL);
1627}
1628
1629#if defined(SPI_I2SCFGR_ASTRTEN)
1636__STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx)
1637{
1638 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
1639}
1640
1647__STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx)
1648{
1649 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN);
1650}
1651
1658__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(const SPI_TypeDef *SPIx)
1659{
1660 return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL);
1661}
1662#endif /* SPI_I2SCFGR_ASTRTEN */
1663
1667
1671
1678__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx)
1679{
1680 return LL_SPI_IsActiveFlag_RXNE(SPIx);
1681}
1682
1689__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx)
1690{
1691 return LL_SPI_IsActiveFlag_TXE(SPIx);
1692}
1693
1700__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx)
1701{
1702 return LL_SPI_IsActiveFlag_BSY(SPIx);
1703}
1704
1711__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx)
1712{
1713 return LL_SPI_IsActiveFlag_OVR(SPIx);
1714}
1715
1722__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx)
1723{
1724 return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);
1725}
1726
1733__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx)
1734{
1735 return LL_SPI_IsActiveFlag_FRE(SPIx);
1736}
1737
1747__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx)
1748{
1749 return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL);
1750}
1751
1758__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)
1759{
1760 LL_SPI_ClearFlag_OVR(SPIx);
1761}
1762
1769__STATIC_INLINE void LL_I2S_ClearFlag_UDR(const SPI_TypeDef *SPIx)
1770{
1771 __IO uint32_t tmpreg;
1772 tmpreg = SPIx->SR;
1773 (void)tmpreg;
1774}
1775
1782__STATIC_INLINE void LL_I2S_ClearFlag_FRE(const SPI_TypeDef *SPIx)
1783{
1784 LL_SPI_ClearFlag_FRE(SPIx);
1785}
1786
1790
1794
1802__STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx)
1803{
1804 LL_SPI_EnableIT_ERR(SPIx);
1805}
1806
1813__STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx)
1814{
1815 LL_SPI_EnableIT_RXNE(SPIx);
1816}
1817
1824__STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx)
1825{
1826 LL_SPI_EnableIT_TXE(SPIx);
1827}
1828
1836__STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx)
1837{
1838 LL_SPI_DisableIT_ERR(SPIx);
1839}
1840
1847__STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx)
1848{
1849 LL_SPI_DisableIT_RXNE(SPIx);
1850}
1851
1858__STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx)
1859{
1860 LL_SPI_DisableIT_TXE(SPIx);
1861}
1862
1869__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx)
1870{
1871 return LL_SPI_IsEnabledIT_ERR(SPIx);
1872}
1873
1880__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx)
1881{
1882 return LL_SPI_IsEnabledIT_RXNE(SPIx);
1883}
1884
1891__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx)
1892{
1893 return LL_SPI_IsEnabledIT_TXE(SPIx);
1894}
1895
1899
1903
1910__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)
1911{
1912 LL_SPI_EnableDMAReq_RX(SPIx);
1913}
1914
1921__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)
1922{
1923 LL_SPI_DisableDMAReq_RX(SPIx);
1924}
1925
1932__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx)
1933{
1934 return LL_SPI_IsEnabledDMAReq_RX(SPIx);
1935}
1936
1943__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)
1944{
1945 LL_SPI_EnableDMAReq_TX(SPIx);
1946}
1947
1954__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)
1955{
1956 LL_SPI_DisableDMAReq_TX(SPIx);
1957}
1958
1965__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx)
1966{
1967 return LL_SPI_IsEnabledDMAReq_TX(SPIx);
1968}
1969
1973
1977
1984__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)
1985{
1986 return LL_SPI_ReceiveData16(SPIx);
1987}
1988
1996__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)
1997{
1998 LL_SPI_TransmitData16(SPIx, TxData);
1999}
2000
2004
2005#if defined(USE_FULL_LL_DRIVER)
2009
2010ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx);
2011ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);
2012void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);
2013void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);
2014#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
2015ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct);
2016#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
2017
2021#endif /* USE_FULL_LL_DRIVER */
2022
2026
2030
2031#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
2032
2036
2037#ifdef __cplusplus
2038}
2039#endif
2040
2041#endif /* STM32F4xx_LL_SPI_H */
2042