STM32F4xx HAL Driver master
STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_ll_spi.c
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1
18#if defined(USE_FULL_LL_DRIVER)
19
20/* Includes ------------------------------------------------------------------*/
21#include "stm32f4xx_ll_spi.h"
22#include "stm32f4xx_ll_bus.h"
23#include "stm32f4xx_ll_rcc.h"
24
25#ifdef USE_FULL_ASSERT
26#include "stm32_assert.h"
27#else
28#define assert_param(expr) ((void)0U)
29#endif /* USE_FULL_ASSERT */
30
34
35#if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6)
36
40
41/* Private types -------------------------------------------------------------*/
42/* Private variables ---------------------------------------------------------*/
43
44/* Private constants ---------------------------------------------------------*/
48/* SPI registers Masks */
49#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \
50 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \
51 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \
52 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \
53 SPI_CR1_BIDIMODE)
57
58/* Private macros ------------------------------------------------------------*/
62#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \
63 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \
64 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \
65 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX))
66
67#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \
68 || ((__VALUE__) == LL_SPI_MODE_SLAVE))
69
70#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \
71 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT))
72
73#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \
74 || ((__VALUE__) == LL_SPI_POLARITY_HIGH))
75
76#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \
77 || ((__VALUE__) == LL_SPI_PHASE_2EDGE))
78
79#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \
80 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \
81 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT))
82
83#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \
84 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \
85 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \
86 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \
87 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \
88 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \
89 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \
90 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256))
91
92#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \
93 || ((__VALUE__) == LL_SPI_MSB_FIRST))
94
95#define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \
96 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE))
97
98#define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U)
99
103
104/* Private function prototypes -----------------------------------------------*/
105
106/* Exported functions --------------------------------------------------------*/
110
114
122ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx)
123{
124 ErrorStatus status = ERROR;
125
126 /* Check the parameters */
127 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
128
129#if defined(SPI1)
130 if (SPIx == SPI1)
131 {
132 /* Force reset of SPI clock */
133 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1);
134
135 /* Release reset of SPI clock */
136 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1);
137
138 status = SUCCESS;
139 }
140#endif /* SPI1 */
141#if defined(SPI2)
142 if (SPIx == SPI2)
143 {
144 /* Force reset of SPI clock */
145 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2);
146
147 /* Release reset of SPI clock */
148 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2);
149
150 status = SUCCESS;
151 }
152#endif /* SPI2 */
153#if defined(SPI3)
154 if (SPIx == SPI3)
155 {
156 /* Force reset of SPI clock */
157 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3);
158
159 /* Release reset of SPI clock */
160 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3);
161
162 status = SUCCESS;
163 }
164#endif /* SPI3 */
165#if defined(SPI4)
166 if (SPIx == SPI4)
167 {
168 /* Force reset of SPI clock */
169 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4);
170
171 /* Release reset of SPI clock */
172 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4);
173
174 status = SUCCESS;
175 }
176#endif /* SPI4 */
177#if defined(SPI5)
178 if (SPIx == SPI5)
179 {
180 /* Force reset of SPI clock */
181 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5);
182
183 /* Release reset of SPI clock */
184 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5);
185
186 status = SUCCESS;
187 }
188#endif /* SPI5 */
189#if defined(SPI6)
190 if (SPIx == SPI6)
191 {
192 /* Force reset of SPI clock */
193 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6);
194
195 /* Release reset of SPI clock */
196 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6);
197
198 status = SUCCESS;
199 }
200#endif /* SPI6 */
201
202 return status;
203}
204
214ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct)
215{
216 ErrorStatus status = ERROR;
217
218 /* Check the SPI Instance SPIx*/
219 assert_param(IS_SPI_ALL_INSTANCE(SPIx));
220
221 /* Check the SPI parameters from SPI_InitStruct*/
222 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection));
223 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode));
224 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth));
225 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity));
226 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase));
227 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS));
228 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate));
229 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder));
230 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation));
231
232 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U)
233 {
234 /*---------------------------- SPIx CR1 Configuration ------------------------
235 * Configure SPIx CR1 with parameters:
236 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits
237 * - Master/Slave Mode: SPI_CR1_MSTR bit
238 * - DataWidth: SPI_CR1_DFF bit
239 * - ClockPolarity: SPI_CR1_CPOL bit
240 * - ClockPhase: SPI_CR1_CPHA bit
241 * - NSS management: SPI_CR1_SSM bit
242 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits
243 * - BitOrder: SPI_CR1_LSBFIRST bit
244 * - CRCCalculation: SPI_CR1_CRCEN bit
245 */
246 MODIFY_REG(SPIx->CR1,
247 SPI_CR1_CLEAR_MASK,
248 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth |
249 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase |
250 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate |
251 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation);
252
253 /*---------------------------- SPIx CR2 Configuration ------------------------
254 * Configure SPIx CR2 with parameters:
255 * - NSS management: SSOE bit
256 */
257 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U));
258
259 /*---------------------------- SPIx CRCPR Configuration ----------------------
260 * Configure SPIx CRCPR with parameters:
261 * - CRCPoly: CRCPOLY[15:0] bits
262 */
263 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE)
264 {
265 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly));
266 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly);
267 }
268 status = SUCCESS;
269 }
270
271 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
272 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);
273 return status;
274}
275
282void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct)
283{
284 /* Set SPI_InitStruct fields to default values */
285 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX;
286 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE;
287 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT;
288 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW;
289 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE;
290 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT;
291 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2;
292 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST;
293 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE;
294 SPI_InitStruct->CRCPoly = 7U;
295}
296
300
304
308
312
313/* Private types -------------------------------------------------------------*/
314/* Private variables ---------------------------------------------------------*/
315/* Private constants ---------------------------------------------------------*/
319/* I2S registers Masks */
320#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \
321 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \
322 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD )
323
324#define I2S_I2SPR_CLEAR_MASK 0x0002U
328/* Private macros ------------------------------------------------------------*/
332
333#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \
334 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \
335 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \
336 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B))
337
338#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \
339 || ((__VALUE__) == LL_I2S_POLARITY_HIGH))
340
341#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \
342 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \
343 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \
344 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \
345 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG))
346
347#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \
348 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \
349 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \
350 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX))
351
352#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \
353 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE))
354
355#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \
356 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \
357 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT))
358
359#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U)
360
361#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \
362 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD))
366
367/* Private function prototypes -----------------------------------------------*/
368
369/* Exported functions --------------------------------------------------------*/
373
377
385ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx)
386{
387 return LL_SPI_DeInit(SPIx);
388}
389
400ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct)
401{
402 uint32_t i2sdiv = 2U;
403 uint32_t i2sodd = 0U;
404 uint32_t packetlength = 1U;
405 uint32_t tmp;
406 uint32_t sourceclock;
407 ErrorStatus status = ERROR;
408
409 /* Check the I2S parameters */
410 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
411 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
412 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
413 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
414 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput));
415 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq));
416 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
417
418 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U)
419 {
420 /*---------------------------- SPIx I2SCFGR Configuration --------------------
421 * Configure SPIx I2SCFGR with parameters:
422 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
423 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
424 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
425 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
426 */
427
428 /* Write to SPIx I2SCFGR */
429 MODIFY_REG(SPIx->I2SCFGR,
430 I2S_I2SCFGR_CLEAR_MASK,
431 I2S_InitStruct->Mode | I2S_InitStruct->Standard |
432 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
433 SPI_I2SCFGR_I2SMOD);
434
435 /*---------------------------- SPIx I2SPR Configuration ----------------------
436 * Configure SPIx I2SPR with parameters:
437 * - MCLKOutput: SPI_I2SPR_MCKOE bit
438 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits
439 */
440
441 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv)
442 * else, default values are used: i2sodd = 0U, i2sdiv = 2U.
443 */
444 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT)
445 {
446 /* Check the frame length (For the Prescaler computing)
447 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U).
448 */
449 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B)
450 {
451 /* Packet length is 32 bits */
452 packetlength = 2U;
453 }
454
455 /* If an external I2S clock has to be used, the specific define should be set
456 in the project configuration or in the stm32f4xx_ll_rcc.h file */
457 /* Get the I2S source clock value */
458 sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE);
459
460 /* Compute the Real divider depending on the MCLK output state with a floating point */
461 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE)
462 {
463 /* MCLK output is enabled */
464 tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
465 }
466 else
467 {
468 /* MCLK output is disabled */
469 tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U);
470 }
471
472 /* Remove the floating point */
473 tmp = tmp / 10U;
474
475 /* Check the parity of the divider */
476 i2sodd = (tmp & (uint16_t)0x0001U);
477
478 /* Compute the i2sdiv prescaler */
479 i2sdiv = ((tmp - i2sodd) / 2U);
480
481 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
482 i2sodd = (i2sodd << 8U);
483 }
484
485 /* Test if the divider is 1 or 0 or greater than 0xFF */
486 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU))
487 {
488 /* Set the default values */
489 i2sdiv = 2U;
490 i2sodd = 0U;
491 }
492
493 /* Write to SPIx I2SPR register the computed value */
494 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput);
495
496 status = SUCCESS;
497 }
498 return status;
499}
500
507void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct)
508{
509 /*--------------- Reset I2S init structure parameters values -----------------*/
510 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX;
511 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS;
512 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B;
513 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE;
514 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT;
515 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW;
516}
517
529void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity)
530{
531 /* Check the I2S parameters */
532 assert_param(IS_I2S_ALL_INSTANCE(SPIx));
533 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear));
534 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity));
535
536 /* Write to SPIx I2SPR */
537 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U));
538}
539
540#if defined (SPI_I2S_FULLDUPLEX_SUPPORT)
555ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct)
556{
557 uint32_t mode = 0U;
558 ErrorStatus status = ERROR;
559
560 /* Check the I2S parameters */
561 assert_param(IS_I2S_EXT_ALL_INSTANCE(I2Sxext));
562 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode));
563 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard));
564 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat));
565 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity));
566
567 if (LL_I2S_IsEnabled(I2Sxext) == 0x00000000U)
568 {
569 /*---------------------------- SPIx I2SCFGR Configuration --------------------
570 * Configure SPIx I2SCFGR with parameters:
571 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit
572 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits
573 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits
574 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit
575 */
576
577 /* Reset I2SPR registers */
578 WRITE_REG(I2Sxext->I2SPR, I2S_I2SPR_CLEAR_MASK);
579
580 /* Get the mode to be configured for the extended I2S */
581 if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_TX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_TX))
582 {
583 mode = LL_I2S_MODE_SLAVE_RX;
584 }
585 else
586 {
587 if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_RX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_RX))
588 {
589 mode = LL_I2S_MODE_SLAVE_TX;
590 }
591 }
592
593 /* Write to SPIx I2SCFGR */
594 MODIFY_REG(I2Sxext->I2SCFGR,
595 I2S_I2SCFGR_CLEAR_MASK,
596 I2S_InitStruct->Standard |
597 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity |
598 SPI_I2SCFGR_I2SMOD | mode);
599
600 status = SUCCESS;
601 }
602 return status;
603}
604#endif /* SPI_I2S_FULLDUPLEX_SUPPORT */
605
609
613
617
618#endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */
619
623
624#endif /* USE_FULL_LL_DRIVER */
625
assert_param
#define assert_param(expr)
Definition stm32_assert_template.h:46
stm32f4xx_ll_bus.h
Header file of BUS LL module.
stm32f4xx_ll_rcc.h
Header file of RCC LL module.
stm32f4xx_ll_spi.h
Header file of SPI LL module.