stm32f4xx_ll_sdmmc.h

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/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32F4xx_LL_SDMMC_H
#define STM32F4xx_LL_SDMMC_H
 
#ifdef __cplusplus
 extern "C" {
#endif
 
#if defined(SDIO)
 
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"

 
 
/* Exported types ------------------------------------------------------------*/ 
  
typedef struct
{
  uint32_t ClockEdge;            
 
  uint32_t ClockBypass;          
 
  uint32_t ClockPowerSave;       
 
  uint32_t BusWide;              
 
  uint32_t HardwareFlowControl;  
 
  uint32_t ClockDiv;               
  
}SDIO_InitTypeDef;
  

typedef struct                                                                                            
{
  uint32_t Argument;            
 
  uint32_t CmdIndex;            
 
  uint32_t Response;            
 
  uint32_t WaitForInterrupt;    
 
  uint32_t CPSM;                
}SDIO_CmdInitTypeDef;
 

typedef struct
{
  uint32_t DataTimeOut;         
 
  uint32_t DataLength;          
 
  uint32_t DataBlockSize;       
 
  uint32_t TransferDir;         
 
  uint32_t TransferMode;        
 
  uint32_t DPSM;                
}SDIO_DataInitTypeDef;

  
/* Exported constants --------------------------------------------------------*/
#define SDMMC_ERROR_NONE                                0x00000000U    
#define SDMMC_ERROR_CMD_CRC_FAIL                        0x00000001U    
#define SDMMC_ERROR_DATA_CRC_FAIL                       0x00000002U    
#define SDMMC_ERROR_CMD_RSP_TIMEOUT                     0x00000004U    
#define SDMMC_ERROR_DATA_TIMEOUT                        0x00000008U    
#define SDMMC_ERROR_TX_UNDERRUN                         0x00000010U    
#define SDMMC_ERROR_RX_OVERRUN                          0x00000020U    
#define SDMMC_ERROR_ADDR_MISALIGNED                     0x00000040U    
#define SDMMC_ERROR_BLOCK_LEN_ERR                       0x00000080U    
#define SDMMC_ERROR_ERASE_SEQ_ERR                       0x00000100U    
#define SDMMC_ERROR_BAD_ERASE_PARAM                     0x00000200U    
#define SDMMC_ERROR_WRITE_PROT_VIOLATION                0x00000400U    
#define SDMMC_ERROR_LOCK_UNLOCK_FAILED                  0x00000800U    
#define SDMMC_ERROR_COM_CRC_FAILED                      0x00001000U    
#define SDMMC_ERROR_ILLEGAL_CMD                         0x00002000U    
#define SDMMC_ERROR_CARD_ECC_FAILED                     0x00004000U    
#define SDMMC_ERROR_CC_ERR                              0x00008000U    
#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR                 0x00010000U    
#define SDMMC_ERROR_STREAM_READ_UNDERRUN                0x00020000U    
#define SDMMC_ERROR_STREAM_WRITE_OVERRUN                0x00040000U    
#define SDMMC_ERROR_CID_CSD_OVERWRITE                   0x00080000U    
#define SDMMC_ERROR_WP_ERASE_SKIP                       0x00100000U    
#define SDMMC_ERROR_CARD_ECC_DISABLED                   0x00200000U    
#define SDMMC_ERROR_ERASE_RESET                         0x00400000U    
#define SDMMC_ERROR_AKE_SEQ_ERR                         0x00800000U    
#define SDMMC_ERROR_INVALID_VOLTRANGE                   0x01000000U    
#define SDMMC_ERROR_ADDR_OUT_OF_RANGE                   0x02000000U    
#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE              0x04000000U    
#define SDMMC_ERROR_INVALID_PARAMETER                   0x08000000U    
#define SDMMC_ERROR_UNSUPPORTED_FEATURE                 0x10000000U    
#define SDMMC_ERROR_BUSY                                0x20000000U    
#define SDMMC_ERROR_DMA                                 0x40000000U    
#define SDMMC_ERROR_TIMEOUT                             0x80000000U    

#define SDMMC_CMD_GO_IDLE_STATE                                 0U    
#define SDMMC_CMD_SEND_OP_COND                                  1U    
#define SDMMC_CMD_ALL_SEND_CID                                  2U    
#define SDMMC_CMD_SET_REL_ADDR                                  3U    
#define SDMMC_CMD_SET_DSR                                       4U    
#define SDMMC_CMD_SDMMC_SEN_OP_COND                             5U    
#define SDMMC_CMD_HS_SWITCH                                     6U    
#define SDMMC_CMD_SEL_DESEL_CARD                                7U    
#define SDMMC_CMD_HS_SEND_EXT_CSD                               8U    
#define SDMMC_CMD_SEND_CSD                                      9U    
#define SDMMC_CMD_SEND_CID                                      10U   
#define SDMMC_CMD_READ_DAT_UNTIL_STOP                           11U   
#define SDMMC_CMD_STOP_TRANSMISSION                             12U   
#define SDMMC_CMD_SEND_STATUS                                   13U   
#define SDMMC_CMD_HS_BUSTEST_READ                               14U   
#define SDMMC_CMD_GO_INACTIVE_STATE                             15U   
#define SDMMC_CMD_SET_BLOCKLEN                                  16U   
#define SDMMC_CMD_READ_SINGLE_BLOCK                             17U   
#define SDMMC_CMD_READ_MULT_BLOCK                               18U   
#define SDMMC_CMD_HS_BUSTEST_WRITE                              19U   
#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP                          20U   
#define SDMMC_CMD_SET_BLOCK_COUNT                               23U   
#define SDMMC_CMD_WRITE_SINGLE_BLOCK                            24U   
#define SDMMC_CMD_WRITE_MULT_BLOCK                              25U   
#define SDMMC_CMD_PROG_CID                                      26U   
#define SDMMC_CMD_PROG_CSD                                      27U   
#define SDMMC_CMD_SET_WRITE_PROT                                28U   
#define SDMMC_CMD_CLR_WRITE_PROT                                29U   
#define SDMMC_CMD_SEND_WRITE_PROT                               30U   
#define SDMMC_CMD_SD_ERASE_GRP_START                            32U   
#define SDMMC_CMD_SD_ERASE_GRP_END                              33U   
#define SDMMC_CMD_ERASE_GRP_START                               35U   
#define SDMMC_CMD_ERASE_GRP_END                                 36U   
#define SDMMC_CMD_ERASE                                         38U   
#define SDMMC_CMD_FAST_IO                                       39U   
#define SDMMC_CMD_GO_IRQ_STATE                                  40U   
#define SDMMC_CMD_LOCK_UNLOCK                                   42U   
#define SDMMC_CMD_APP_CMD                                       55U   
#define SDMMC_CMD_GEN_CMD                                       56U   
#define SDMMC_CMD_NO_CMD                                        64U   

#define SDMMC_CMD_APP_SD_SET_BUSWIDTH                           6U    
#define SDMMC_CMD_SD_APP_STATUS                                 13U   
#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS                  22U   
#define SDMMC_CMD_SD_APP_OP_COND                                41U   
#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT                    42U   
#define SDMMC_CMD_SD_APP_SEND_SCR                               51U   
#define SDMMC_CMD_SDMMC_RW_DIRECT                               52U   
#define SDMMC_CMD_SDMMC_RW_EXTENDED                             53U   

#define SDMMC_CMD_SD_APP_GET_MKB                                43U
#define SDMMC_CMD_SD_APP_GET_MID                                44U
#define SDMMC_CMD_SD_APP_SET_CER_RN1                            45U
#define SDMMC_CMD_SD_APP_GET_CER_RN2                            46U
#define SDMMC_CMD_SD_APP_SET_CER_RES2                           47U
#define SDMMC_CMD_SD_APP_GET_CER_RES1                           48U
#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK             18U
#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK            25U
#define SDMMC_CMD_SD_APP_SECURE_ERASE                           38U
#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA                     49U
#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB                       48U

#define SDMMC_OCR_ADDR_OUT_OF_RANGE                   0x80000000U
#define SDMMC_OCR_ADDR_MISALIGNED                     0x40000000U
#define SDMMC_OCR_BLOCK_LEN_ERR                       0x20000000U
#define SDMMC_OCR_ERASE_SEQ_ERR                       0x10000000U
#define SDMMC_OCR_BAD_ERASE_PARAM                     0x08000000U
#define SDMMC_OCR_WRITE_PROT_VIOLATION                0x04000000U
#define SDMMC_OCR_LOCK_UNLOCK_FAILED                  0x01000000U
#define SDMMC_OCR_COM_CRC_FAILED                      0x00800000U
#define SDMMC_OCR_ILLEGAL_CMD                         0x00400000U
#define SDMMC_OCR_CARD_ECC_FAILED                     0x00200000U
#define SDMMC_OCR_CC_ERROR                            0x00100000U
#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR               0x00080000U
#define SDMMC_OCR_STREAM_READ_UNDERRUN                0x00040000U
#define SDMMC_OCR_STREAM_WRITE_OVERRUN                0x00020000U
#define SDMMC_OCR_CID_CSD_OVERWRITE                   0x00010000U
#define SDMMC_OCR_WP_ERASE_SKIP                       0x00008000U
#define SDMMC_OCR_CARD_ECC_DISABLED                   0x00004000U
#define SDMMC_OCR_ERASE_RESET                         0x00002000U
#define SDMMC_OCR_AKE_SEQ_ERROR                       0x00000008U
#define SDMMC_OCR_ERRORBITS                           0xFDFFE008U

#define SDMMC_R6_GENERAL_UNKNOWN_ERROR                0x00002000U
#define SDMMC_R6_ILLEGAL_CMD                          0x00004000U
#define SDMMC_R6_COM_CRC_FAILED                       0x00008000U
 
#define SDMMC_VOLTAGE_WINDOW_SD                       0x80100000U
#define SDMMC_HIGH_CAPACITY                           0x40000000U
#define SDMMC_STD_CAPACITY                            0x00000000U
#define SDMMC_CHECK_PATTERN                           0x000001AAU
#define SD_SWITCH_1_8V_CAPACITY                       0x01000000U
 
#define SDMMC_MAX_VOLT_TRIAL                          0x0000FFFFU
 
#define SDMMC_MAX_TRIAL                               0x0000FFFFU
 
#define SDMMC_ALLZERO                                 0x00000000U
 
#define SDMMC_WIDE_BUS_SUPPORT                        0x00040000U
#define SDMMC_SINGLE_BUS_SUPPORT                      0x00010000U
#define SDMMC_CARD_LOCKED                             0x02000000U
 
#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */
#define SDMMC_DATATIMEOUT                  ((uint32_t)0xFFFFFFFFU)
#endif /* SDMMC_DATATIMEOUT */
 
#ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */
#define SDMMC_SWDATATIMEOUT                SDMMC_DATATIMEOUT
#endif /* SDMMC_SWDATATIMEOUT */
 
#define SDMMC_0TO7BITS                                0x000000FFU
#define SDMMC_8TO15BITS                               0x0000FF00U
#define SDMMC_16TO23BITS                              0x00FF0000U
#define SDMMC_24TO31BITS                              0xFF000000U
#define SDMMC_MAX_DATA_LENGTH                         0x01FFFFFFU
 
#define SDMMC_HALFFIFO                                0x00000008U
#define SDMMC_HALFFIFOBYTES                           0x00000020U

#define SDIO_CCCC_ERASE                       0x00000020U
 
#define SDIO_CMDTIMEOUT                       5000U         /* Command send and response timeout */
#define SDIO_MAXERASETIMEOUT                  63000U        /* Max erase Timeout 63 s            */
#define SDIO_STOPTRANSFERTIMEOUT              100000000U    /* Timeout for STOP TRANSMISSION command */

#define SDIO_CLOCK_EDGE_RISING               0x00000000U
#define SDIO_CLOCK_EDGE_FALLING              SDIO_CLKCR_NEGEDGE
 
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
                                          ((EDGE) == SDIO_CLOCK_EDGE_FALLING))

#define SDIO_CLOCK_BYPASS_DISABLE             0x00000000U
#define SDIO_CLOCK_BYPASS_ENABLE              SDIO_CLKCR_BYPASS   
 
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
                                              ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) 

#define SDIO_CLOCK_POWER_SAVE_DISABLE         0x00000000U
#define SDIO_CLOCK_POWER_SAVE_ENABLE          SDIO_CLKCR_PWRSAV
 
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
                                                ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))

#define SDIO_BUS_WIDE_1B                      0x00000000U
#define SDIO_BUS_WIDE_4B                      SDIO_CLKCR_WIDBUS_0
#define SDIO_BUS_WIDE_8B                      SDIO_CLKCR_WIDBUS_1
 
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
                                        ((WIDE) == SDIO_BUS_WIDE_4B) || \
                                        ((WIDE) == SDIO_BUS_WIDE_8B))

#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    0x00000000U
#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE     SDIO_CLKCR_HWFC_EN
 
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
                                                        ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
  
#define IS_SDIO_CLKDIV(DIV)   ((DIV) <= 0xFFU)  
    
#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40U)

#define SDIO_RESPONSE_NO                    0x00000000U
#define SDIO_RESPONSE_SHORT                 SDIO_CMD_WAITRESP_0
#define SDIO_RESPONSE_LONG                  SDIO_CMD_WAITRESP
 
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO)    || \
                                            ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
                                            ((RESPONSE) == SDIO_RESPONSE_LONG))

#define SDIO_WAIT_NO                        0x00000000U
#define SDIO_WAIT_IT                        SDIO_CMD_WAITINT 
#define SDIO_WAIT_PEND                      SDIO_CMD_WAITPEND
 
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
                                    ((WAIT) == SDIO_WAIT_IT) || \
                                    ((WAIT) == SDIO_WAIT_PEND))

#define SDIO_CPSM_DISABLE                   0x00000000U
#define SDIO_CPSM_ENABLE                    SDIO_CMD_CPSMEN
 
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
                                    ((CPSM) == SDIO_CPSM_ENABLE))  

#define SDIO_RESP1                          0x00000000U
#define SDIO_RESP2                          0x00000004U
#define SDIO_RESP3                          0x00000008U
#define SDIO_RESP4                          0x0000000CU
 
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
                                    ((RESP) == SDIO_RESP2) || \
                                    ((RESP) == SDIO_RESP3) || \
                                    ((RESP) == SDIO_RESP4))

#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)

#define SDIO_DATABLOCK_SIZE_1B               0x00000000U
#define SDIO_DATABLOCK_SIZE_2B               SDIO_DCTRL_DBLOCKSIZE_0
#define SDIO_DATABLOCK_SIZE_4B               SDIO_DCTRL_DBLOCKSIZE_1
#define SDIO_DATABLOCK_SIZE_8B               (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1)
#define SDIO_DATABLOCK_SIZE_16B              SDIO_DCTRL_DBLOCKSIZE_2
#define SDIO_DATABLOCK_SIZE_32B              (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2)
#define SDIO_DATABLOCK_SIZE_64B              (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
#define SDIO_DATABLOCK_SIZE_128B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2)
#define SDIO_DATABLOCK_SIZE_256B             SDIO_DCTRL_DBLOCKSIZE_3
#define SDIO_DATABLOCK_SIZE_512B             (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_3)
#define SDIO_DATABLOCK_SIZE_1024B            (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3)
#define SDIO_DATABLOCK_SIZE_2048B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_3) 
#define SDIO_DATABLOCK_SIZE_4096B            (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
#define SDIO_DATABLOCK_SIZE_8192B            (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
#define SDIO_DATABLOCK_SIZE_16384B           (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3)
 
#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B)    || \
                                          ((SIZE) == SDIO_DATABLOCK_SIZE_2B)    || \
                                          ((SIZE) == SDIO_DATABLOCK_SIZE_4B)    || \
                                          ((SIZE) == SDIO_DATABLOCK_SIZE_8B)    || \
                                          ((SIZE) == SDIO_DATABLOCK_SIZE_16B)   || \
                                          ((SIZE) == SDIO_DATABLOCK_SIZE_32B)   || \
                                          ((SIZE) == SDIO_DATABLOCK_SIZE_64B)   || \
                                          ((SIZE) == SDIO_DATABLOCK_SIZE_128B)  || \
                                          ((SIZE) == SDIO_DATABLOCK_SIZE_256B)  || \
                                          ((SIZE) == SDIO_DATABLOCK_SIZE_512B)  || \
                                          ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
                                          ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
                                          ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
                                          ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
                                          ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) 

#define SDIO_TRANSFER_DIR_TO_CARD            0x00000000U
#define SDIO_TRANSFER_DIR_TO_SDIO    SDIO_DCTRL_DTDIR
 
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
                                           ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))

#define SDIO_TRANSFER_MODE_BLOCK             0x00000000U
#define SDIO_TRANSFER_MODE_STREAM            SDIO_DCTRL_DTMODE
 
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
                                             ((MODE) == SDIO_TRANSFER_MODE_STREAM))

#define SDIO_DPSM_DISABLE                    0x00000000U
#define SDIO_DPSM_ENABLE                     SDIO_DCTRL_DTEN
 
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
                                    ((DPSM) == SDIO_DPSM_ENABLE))
  
#define SDIO_READ_WAIT_MODE_DATA2                0x00000000U
#define SDIO_READ_WAIT_MODE_CLK                  (SDIO_DCTRL_RWMOD)
 
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
                                             ((MODE) == SDIO_READ_WAIT_MODE_DATA2))  

#define SDIO_IT_CCRCFAIL                    SDIO_MASK_CCRCFAILIE
#define SDIO_IT_DCRCFAIL                    SDIO_MASK_DCRCFAILIE
#define SDIO_IT_CTIMEOUT                    SDIO_MASK_CTIMEOUTIE
#define SDIO_IT_DTIMEOUT                    SDIO_MASK_DTIMEOUTIE
#define SDIO_IT_TXUNDERR                    SDIO_MASK_TXUNDERRIE
#define SDIO_IT_RXOVERR                     SDIO_MASK_RXOVERRIE
#define SDIO_IT_CMDREND                     SDIO_MASK_CMDRENDIE
#define SDIO_IT_CMDSENT                     SDIO_MASK_CMDSENTIE
#define SDIO_IT_DATAEND                     SDIO_MASK_DATAENDIE
#if defined(SDIO_STA_STBITERR)
#define SDIO_IT_STBITERR                    SDIO_MASK_STBITERRIE
#endif
#define SDIO_IT_DBCKEND                     SDIO_MASK_DBCKENDIE
#define SDIO_IT_CMDACT                      SDIO_MASK_CMDACTIE
#define SDIO_IT_TXACT                       SDIO_MASK_TXACTIE
#define SDIO_IT_RXACT                       SDIO_MASK_RXACTIE
#define SDIO_IT_TXFIFOHE                    SDIO_MASK_TXFIFOHEIE
#define SDIO_IT_RXFIFOHF                    SDIO_MASK_RXFIFOHFIE
#define SDIO_IT_TXFIFOF                     SDIO_MASK_TXFIFOFIE
#define SDIO_IT_RXFIFOF                     SDIO_MASK_RXFIFOFIE
#define SDIO_IT_TXFIFOE                     SDIO_MASK_TXFIFOEIE
#define SDIO_IT_RXFIFOE                     SDIO_MASK_RXFIFOEIE
#define SDIO_IT_TXDAVL                      SDIO_MASK_TXDAVLIE
#define SDIO_IT_RXDAVL                      SDIO_MASK_RXDAVLIE
#define SDIO_IT_SDIOIT                      SDIO_MASK_SDIOITIE
#if defined(SDIO_CMD_CEATACMD)
#define SDIO_IT_CEATAEND                    SDIO_MASK_CEATAENDIE
#endif 

#define SDIO_FLAG_CCRCFAIL                  SDIO_STA_CCRCFAIL
#define SDIO_FLAG_DCRCFAIL                  SDIO_STA_DCRCFAIL
#define SDIO_FLAG_CTIMEOUT                  SDIO_STA_CTIMEOUT
#define SDIO_FLAG_DTIMEOUT                  SDIO_STA_DTIMEOUT
#define SDIO_FLAG_TXUNDERR                  SDIO_STA_TXUNDERR
#define SDIO_FLAG_RXOVERR                   SDIO_STA_RXOVERR
#define SDIO_FLAG_CMDREND                   SDIO_STA_CMDREND
#define SDIO_FLAG_CMDSENT                   SDIO_STA_CMDSENT
#define SDIO_FLAG_DATAEND                   SDIO_STA_DATAEND
#if defined(SDIO_STA_STBITERR)
#define SDIO_FLAG_STBITERR                  SDIO_STA_STBITERR
#endif
#define SDIO_FLAG_DBCKEND                   SDIO_STA_DBCKEND
#define SDIO_FLAG_CMDACT                    SDIO_STA_CMDACT
#define SDIO_FLAG_TXACT                     SDIO_STA_TXACT
#define SDIO_FLAG_RXACT                     SDIO_STA_RXACT
#define SDIO_FLAG_TXFIFOHE                  SDIO_STA_TXFIFOHE
#define SDIO_FLAG_RXFIFOHF                  SDIO_STA_RXFIFOHF
#define SDIO_FLAG_TXFIFOF                   SDIO_STA_TXFIFOF
#define SDIO_FLAG_RXFIFOF                   SDIO_STA_RXFIFOF
#define SDIO_FLAG_TXFIFOE                   SDIO_STA_TXFIFOE
#define SDIO_FLAG_RXFIFOE                   SDIO_STA_RXFIFOE
#define SDIO_FLAG_TXDAVL                    SDIO_STA_TXDAVL
#define SDIO_FLAG_RXDAVL                    SDIO_STA_RXDAVL
#define SDIO_FLAG_SDIOIT                    SDIO_STA_SDIOIT
#if defined(SDIO_CMD_CEATACMD)
#define SDIO_FLAG_CEATAEND                  SDIO_STA_CEATAEND
#endif
#define SDIO_STATIC_FLAGS                   ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
                                                         SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR  |\
                                                         SDIO_FLAG_CMDREND  | SDIO_FLAG_CMDSENT  | SDIO_FLAG_DATAEND  |\
                                                         SDIO_FLAG_DBCKEND | SDIO_FLAG_SDIOIT))  
 
#define SDIO_STATIC_CMD_FLAGS               ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND |\
                                                         SDIO_FLAG_CMDSENT))
 
#define SDIO_STATIC_DATA_FLAGS              ((uint32_t)(SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR |\
                                                         SDIO_FLAG_RXOVERR  | SDIO_FLAG_DATAEND  | SDIO_FLAG_DBCKEND))

  
/* Exported macro ------------------------------------------------------------*/

/* ------------ SDIO registers bit address in the alias region -------------- */
#define SDIO_OFFSET               (SDIO_BASE - PERIPH_BASE)
 
/* --- CLKCR Register ---*/
/* Alias word address of CLKEN bit */
#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04U)
#define CLKEN_BITNUMBER           0x08U
#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32U) + (CLKEN_BITNUMBER * 4U))
 
/* --- CMD Register ---*/
/* Alias word address of SDIOSUSPEND bit */
#define CMD_OFFSET                (SDIO_OFFSET + 0x0CU)
#define SDIOSUSPEND_BITNUMBER     0x0BU
#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (SDIOSUSPEND_BITNUMBER * 4U))
 
/* Alias word address of ENCMDCOMPL bit */
#define ENCMDCOMPL_BITNUMBER      0x0CU
#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ENCMDCOMPL_BITNUMBER * 4U))
 
/* Alias word address of NIEN bit */
#define NIEN_BITNUMBER            0x0DU
#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (NIEN_BITNUMBER * 4U))
 
/* Alias word address of ATACMD bit */
#define ATACMD_BITNUMBER          0x0EU
#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32U) + (ATACMD_BITNUMBER * 4U))
 
/* --- DCTRL Register ---*/
/* Alias word address of DMAEN bit */
#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2CU)
#define DMAEN_BITNUMBER           0x03U
#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (DMAEN_BITNUMBER * 4U))
 
/* Alias word address of RWSTART bit */
#define RWSTART_BITNUMBER         0x08U
#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTART_BITNUMBER * 4U))
 
/* Alias word address of RWSTOP bit */
#define RWSTOP_BITNUMBER          0x09U
#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWSTOP_BITNUMBER * 4U))
 
/* Alias word address of RWMOD bit */
#define RWMOD_BITNUMBER           0x0AU
#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (RWMOD_BITNUMBER * 4U))
 
/* Alias word address of SDIOEN bit */
#define SDIOEN_BITNUMBER          0x0BU
#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32U) + (SDIOEN_BITNUMBER * 4U))

/* ---------------------- SDIO registers bit mask --------------------------- */
/* --- CLKCR Register ---*/
/* CLKCR register clear mask */ 
#define CLKCR_CLEAR_MASK         ((uint32_t)(SDIO_CLKCR_CLKDIV  | SDIO_CLKCR_PWRSAV |\
                                             SDIO_CLKCR_BYPASS  | SDIO_CLKCR_WIDBUS |\
                                             SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
 
/* --- DCTRL Register ---*/
/* SDIO DCTRL Clear Mask */
#define DCTRL_CLEAR_MASK         ((uint32_t)(SDIO_DCTRL_DTEN    | SDIO_DCTRL_DTDIR |\
                                             SDIO_DCTRL_DTMODE  | SDIO_DCTRL_DBLOCKSIZE))
 
/* --- CMD Register ---*/
/* CMD Register clear mask */
#define CMD_CLEAR_MASK           ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
                                             SDIO_CMD_WAITINT  | SDIO_CMD_WAITPEND |\
                                             SDIO_CMD_CPSMEN   | SDIO_CMD_SDIOSUSPEND))
 
/* SDIO Initialization Frequency (400KHz max) */
#define SDIO_INIT_CLK_DIV     ((uint8_t)0x76)    /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */
 
/* SDIO Data Transfer Frequency (25MHz max) */
#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)     /* 48MHz / (SDMMC_TRANSFER_CLK_DIV + 2) < 25MHz */

 
#define __SDIO_ENABLE(__INSTANCE__)  (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)

#define __SDIO_DISABLE(__INSTANCE__)  (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)

#define __SDIO_DMA_ENABLE(__INSTANCE__)  (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)

#define __SDIO_DMA_DISABLE(__INSTANCE__)  (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
 
#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))

#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))

#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != 0U)
 

#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))

#define __SDIO_GET_IT  (__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))

#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))

#define __SDIO_START_READWAIT_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)

#define __SDIO_START_READWAIT_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)

#define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)

#define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)

#define __SDIO_OPERATION_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)

#define __SDIO_OPERATION_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)

#define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__)  (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)

#define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__)  (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
 
#if defined(SDIO_CMD_CEATACMD)    
#define __SDIO_CEATA_CMD_COMPLETION_ENABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
  
#define __SDIO_CEATA_CMD_COMPLETION_DISABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
    
#define __SDIO_CEATA_ENABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0U)
  
#define __SDIO_CEATA_DISABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1U)
  
#define __SDIO_CEATA_SENDCMD_ENABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
  
#define __SDIO_CEATA_SENDCMD_DISABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
   
#endif
  
 
/* Exported functions --------------------------------------------------------*/
  
/* Initialization/de-initialization functions  **********************************/
HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
  
/* I/O operation functions  *****************************************************/
uint32_t          SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
  
/* Peripheral Control functions  ************************************************/
HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
uint32_t          SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
 
/* Command path state machine (CPSM) management functions */
HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *Command);
uint8_t           SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
uint32_t          SDIO_GetResponse(SDIO_TypeDef *SDIOx, uint32_t Response);
 
/* Data path state machine (DPSM) management functions */
HAL_StatusTypeDef SDIO_ConfigData(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* Data);
uint32_t          SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
uint32_t          SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
 
/* SDMMC Cards mode management functions */
HAL_StatusTypeDef SDIO_SetSDMMCReadWaitMode(SDIO_TypeDef *SDIOx, uint32_t SDIO_ReadWaitMode);
 
/* SDMMC Commands management functions */
uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize);
uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd);
uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd);
uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd);
uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd);
uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr);
uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth);
uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA);
uint32_t SDMMC_CmdSetRelAddMmc(SDIO_TypeDef *SDIOx, uint16_t RCA);
uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument);
uint32_t SDMMC_CmdSendEXTCSD(SDIO_TypeDef *SDIOx, uint32_t Argument);
 
/* SDMMC Responses management functions *****************************************/
uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout);
uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx);
uint32_t SDMMC_GetCmdResp6(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint16_t *pRCA);
uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx);
  
   

 
#endif /* SDIO */
 
#ifdef __cplusplus
}
#endif
 
#endif /* STM32F4xx_LL_SDMMC_H */