STM32F4xx HAL Driver master
STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_ll_rcc.h
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1
17
18/* Define to prevent recursive inclusion -------------------------------------*/
19#ifndef __STM32F4xx_LL_RCC_H
20#define __STM32F4xx_LL_RCC_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26/* Includes ------------------------------------------------------------------*/
27#include "stm32f4xx.h"
28
32
33#if defined(RCC)
34
38
39/* Private types -------------------------------------------------------------*/
40/* Private variables ---------------------------------------------------------*/
44
45#if defined(RCC_PLLSAI_SUPPORT) && defined(LTDC)
46static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
47#endif /* RCC_PLLSAI_SUPPORT && LTDC */
48
52/* Private constants ---------------------------------------------------------*/
53/* Private macros ------------------------------------------------------------*/
54#if defined(USE_FULL_LL_DRIVER)
61#endif /*USE_FULL_LL_DRIVER*/
62/* Exported types ------------------------------------------------------------*/
63#if defined(USE_FULL_LL_DRIVER)
67
71
75typedef struct
76{
77 uint32_t SYSCLK_Frequency;
78 uint32_t HCLK_Frequency;
79 uint32_t PCLK1_Frequency;
80 uint32_t PCLK2_Frequency;
81} LL_RCC_ClocksTypeDef;
82
86
90#endif /* USE_FULL_LL_DRIVER */
91
92/* Exported constants --------------------------------------------------------*/
96
103#if !defined (HSE_VALUE)
104#define HSE_VALUE 25000000U
105#endif /* HSE_VALUE */
106
107#if !defined (HSI_VALUE)
108#define HSI_VALUE 16000000U
109#endif /* HSI_VALUE */
110
111#if !defined (LSE_VALUE)
112#define LSE_VALUE 32768U
113#endif /* LSE_VALUE */
114
115#if !defined (LSI_VALUE)
116#define LSI_VALUE 32000U
117#endif /* LSI_VALUE */
118
119#if !defined (EXTERNAL_CLOCK_VALUE)
120#define EXTERNAL_CLOCK_VALUE 12288000U
121#endif /* EXTERNAL_CLOCK_VALUE */
125
130#define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC
131#define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC
132#define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC
133#define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC
134#define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC
135#if defined(RCC_PLLI2S_SUPPORT)
136#define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC
137#endif /* RCC_PLLI2S_SUPPORT */
138#if defined(RCC_PLLSAI_SUPPORT)
139#define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC
140#endif /* RCC_PLLSAI_SUPPORT */
141#define LL_RCC_CIR_CSSC RCC_CIR_CSSC
145
150#define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF
151#define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF
152#define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF
153#define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF
154#define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF
155#if defined(RCC_PLLI2S_SUPPORT)
156#define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF
157#endif /* RCC_PLLI2S_SUPPORT */
158#if defined(RCC_PLLSAI_SUPPORT)
159#define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF
160#endif /* RCC_PLLSAI_SUPPORT */
161#define LL_RCC_CIR_CSSF RCC_CIR_CSSF
162#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF
163#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF
164#define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF
165#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF
166#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF
167#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF
168#if defined(RCC_CSR_BORRSTF)
169#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF
170#endif /* RCC_CSR_BORRSTF */
174
179#define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE
180#define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE
181#define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE
182#define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE
183#define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE
184#if defined(RCC_PLLI2S_SUPPORT)
185#define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE
186#endif /* RCC_PLLI2S_SUPPORT */
187#if defined(RCC_PLLSAI_SUPPORT)
188#define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE
189#endif /* RCC_PLLSAI_SUPPORT */
193
197#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
198#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
199#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL
200#if defined(RCC_CFGR_SW_PLLR)
201#define LL_RCC_SYS_CLKSOURCE_PLLR RCC_CFGR_SW_PLLR
202#endif /* RCC_CFGR_SW_PLLR */
206
210#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
211#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
212#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL
213#if defined(RCC_PLLR_SYSCLK_SUPPORT)
214#define LL_RCC_SYS_CLKSOURCE_STATUS_PLLR RCC_CFGR_SWS_PLLR
215#endif /* RCC_PLLR_SYSCLK_SUPPORT */
219
223#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1
224#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2
225#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4
226#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8
227#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16
228#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64
229#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128
230#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256
231#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512
235
239#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1
240#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2
241#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4
242#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8
243#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16
247
251#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1
252#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2
253#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4
254#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8
255#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16
259
263#define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U)
264#define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U))
265#define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U))
266#define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U))
267#if defined(RCC_CFGR_MCO2)
268#define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U)
269#define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U))
270#define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U))
271#define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U))
272#endif /* RCC_CFGR_MCO2 */
276
280#define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U)
281#define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U))
282#define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U))
283#define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U))
284#define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U))
285#if defined(RCC_CFGR_MCO2PRE)
286#define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U)
287#define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U))
288#define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U))
289#define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U))
290#define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U))
291#endif /* RCC_CFGR_MCO2PRE */
295
299#define LL_RCC_RTC_NOCLOCK 0x00000000U
300#define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1
301#define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
302#define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2
303#define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
304#define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
305#define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
306#define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3
307#define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
308#define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
309#define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
310#define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
311#define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
312#define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
313#define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
314#define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4
315#define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
316#define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
317#define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
318#define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
319#define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
320#define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
321#define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
322#define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
323#define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
324#define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
325#define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
326#define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
327#define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
328#define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
329#define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
333
334#if defined(USE_FULL_LL_DRIVER)
338#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U
339#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU
343#endif /* USE_FULL_LL_DRIVER */
344
345#if defined(FMPI2C1)
349#define LL_RCC_FMPI2C1_CLKSOURCE_PCLK1 0x00000000U
350#define LL_RCC_FMPI2C1_CLKSOURCE_SYSCLK RCC_DCKCFGR2_FMPI2C1SEL_0
351#define LL_RCC_FMPI2C1_CLKSOURCE_HSI RCC_DCKCFGR2_FMPI2C1SEL_1
355#endif /* FMPI2C1 */
356
357#if defined(LPTIM1)
361#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U
362#define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_0
363#define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_1
364#define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0)
368#endif /* LPTIM1 */
369
370#if defined(SAI1)
374#if defined(RCC_DCKCFGR_SAI1SRC)
375#define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1SRC | 0x00000000U)
376#define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_0 >> 16))
377#define LL_RCC_SAI1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC_1 >> 16))
378#define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1SRC | (RCC_DCKCFGR_SAI1SRC >> 16))
379#endif /* RCC_DCKCFGR_SAI1SRC */
380#if defined(RCC_DCKCFGR_SAI2SRC)
381#define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI2SRC | 0x00000000U)
382#define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_0 >> 16))
383#define LL_RCC_SAI2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC_1 >> 16))
384#define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI2SRC | (RCC_DCKCFGR_SAI2SRC >> 16))
385#endif /* RCC_DCKCFGR_SAI2SRC */
386#if defined(RCC_DCKCFGR_SAI1ASRC)
387#if defined(RCC_SAI1A_PLLSOURCE_SUPPORT)
388#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U)
389#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16))
390#define LL_RCC_SAI1_A_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16))
391#define LL_RCC_SAI1_A_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC >> 16))
392#else
393#define LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U)
394#define LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16))
395#define LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16))
396#endif /* RCC_SAI1A_PLLSOURCE_SUPPORT */
397#endif /* RCC_DCKCFGR_SAI1ASRC */
398#if defined(RCC_DCKCFGR_SAI1BSRC)
399#if defined(RCC_SAI1B_PLLSOURCE_SUPPORT)
400#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U)
401#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16))
402#define LL_RCC_SAI1_B_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16))
403#define LL_RCC_SAI1_B_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC >> 16))
404#else
405#define LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U)
406#define LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16))
407#define LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16))
408#endif /* RCC_SAI1B_PLLSOURCE_SUPPORT */
409#endif /* RCC_DCKCFGR_SAI1BSRC */
413#endif /* SAI1 */
414
415#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
419#define LL_RCC_SDIO_CLKSOURCE_PLL48CLK 0x00000000U
420#if defined(RCC_DCKCFGR_SDIOSEL)
421#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR_SDIOSEL
422#else
423#define LL_RCC_SDIO_CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDIOSEL
424#endif /* RCC_DCKCFGR_SDIOSEL */
428#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
429
430#if defined(DSI)
434#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U
435#define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR_DSISEL
439#endif /* DSI */
440
441#if defined(CEC)
445#define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 0x00000000U
446#define LL_RCC_CEC_CLKSOURCE_LSE RCC_DCKCFGR2_CECSEL
450#endif /* CEC */
451
455#if defined(RCC_CFGR_I2SSRC)
456#define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U
457#define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC
458#endif /* RCC_CFGR_I2SSRC */
459#if defined(RCC_DCKCFGR_I2SSRC)
460#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2SSRC | 0x00000000U)
461#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_0 >> 16))
462#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2SSRC | (RCC_DCKCFGR_I2SSRC_1 >> 16))
463#endif /* RCC_DCKCFGR_I2SSRC */
464#if defined(RCC_DCKCFGR_I2S1SRC)
465#define LL_RCC_I2S1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S1SRC | 0x00000000U)
466#define LL_RCC_I2S1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_0 >> 16))
467#define LL_RCC_I2S1_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC_1 >> 16))
468#define LL_RCC_I2S1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S1SRC | (RCC_DCKCFGR_I2S1SRC >> 16))
469#endif /* RCC_DCKCFGR_I2S1SRC */
470#if defined(RCC_DCKCFGR_I2S2SRC)
471#define LL_RCC_I2S2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_I2S2SRC | 0x00000000U)
472#define LL_RCC_I2S2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_0 >> 16))
473#define LL_RCC_I2S2_CLKSOURCE_PLL (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC_1 >> 16))
474#define LL_RCC_I2S2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR_I2S2SRC | (RCC_DCKCFGR_I2S2SRC >> 16))
475#endif /* RCC_DCKCFGR_I2S2SRC */
479
480#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
484#if defined(RCC_DCKCFGR_CK48MSEL)
485#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U
486#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR_CK48MSEL
487#endif /* RCC_DCKCFGR_CK48MSEL */
488#if defined(RCC_DCKCFGR2_CK48MSEL)
489#define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U
490#if defined(RCC_PLLSAI_SUPPORT)
491#define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL
492#endif /* RCC_PLLSAI_SUPPORT */
493#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
494#define LL_RCC_CK48M_CLKSOURCE_PLLI2S RCC_DCKCFGR2_CK48MSEL
495#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
496#endif /* RCC_DCKCFGR2_CK48MSEL */
500
501#if defined(RNG)
505#define LL_RCC_RNG_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL
506#if defined(RCC_PLLSAI_SUPPORT)
507#define LL_RCC_RNG_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI
508#endif /* RCC_PLLSAI_SUPPORT */
509#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
510#define LL_RCC_RNG_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S
511#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
515#endif /* RNG */
516
517#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
521#define LL_RCC_USB_CLKSOURCE_PLL LL_RCC_CK48M_CLKSOURCE_PLL
522#if defined(RCC_PLLSAI_SUPPORT)
523#define LL_RCC_USB_CLKSOURCE_PLLSAI LL_RCC_CK48M_CLKSOURCE_PLLSAI
524#endif /* RCC_PLLSAI_SUPPORT */
525#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
526#define LL_RCC_USB_CLKSOURCE_PLLI2S LL_RCC_CK48M_CLKSOURCE_PLLI2S
527#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
531#endif /* USB_OTG_FS || USB_OTG_HS */
532
533#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
534
535#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
539#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | 0x00000000U)
540#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM1ASEL | (RCC_DCKCFGR_CKDFSDM1ASEL << 16))
541#if defined(DFSDM2_Channel0)
542#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S1 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | 0x00000000U)
543#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE_I2S2 (uint32_t)(RCC_DCKCFGR_CKDFSDM2ASEL | (RCC_DCKCFGR_CKDFSDM2ASEL << 16))
544#endif /* DFSDM2_Channel0 */
548
552#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U
553#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL
554#if defined(DFSDM2_Channel0)
555#define LL_RCC_DFSDM2_CLKSOURCE_PCLK2 0x00000000U
556#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK RCC_DCKCFGR_CKDFSDM1SEL
557#endif /* DFSDM2_Channel0 */
561#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
562
563#if defined(FMPI2C1)
567#define LL_RCC_FMPI2C1_CLKSOURCE RCC_DCKCFGR2_FMPI2C1SEL
571#endif /* FMPI2C1 */
572
573#if defined(SPDIFRX)
577#define LL_RCC_SPDIFRX1_CLKSOURCE_PLL 0x00000000U
578#define LL_RCC_SPDIFRX1_CLKSOURCE_PLLI2S RCC_DCKCFGR2_SPDIFRXSEL
582#endif /* SPDIFRX */
583
584#if defined(LPTIM1)
588#define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL
592#endif /* LPTIM1 */
593
594#if defined(SAI1)
598#if defined(RCC_DCKCFGR_SAI1ASRC)
599#define LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC
600#endif /* RCC_DCKCFGR_SAI1ASRC */
601#if defined(RCC_DCKCFGR_SAI1BSRC)
602#define LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC
603#endif /* RCC_DCKCFGR_SAI1BSRC */
604#if defined(RCC_DCKCFGR_SAI1SRC)
605#define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR_SAI1SRC
606#endif /* RCC_DCKCFGR_SAI1SRC */
607#if defined(RCC_DCKCFGR_SAI2SRC)
608#define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR_SAI2SRC
609#endif /* RCC_DCKCFGR_SAI2SRC */
613#endif /* SAI1 */
614
615#if defined(SDIO)
619#if defined(RCC_DCKCFGR_SDIOSEL)
620#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR_SDIOSEL
621#elif defined(RCC_DCKCFGR2_SDIOSEL)
622#define LL_RCC_SDIO_CLKSOURCE RCC_DCKCFGR2_SDIOSEL
623#else
624#define LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ
625#endif /* RCC_DCKCFGR_SDIOSEL */
629#endif /* SDIO */
630
631#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
635#if defined(RCC_DCKCFGR_CK48MSEL)
636#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR_CK48MSEL
637#endif /* RCC_DCKCFGR_CK48MSEL */
638#if defined(RCC_DCKCFGR2_CK48MSEL)
639#define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL
640#endif /* RCC_DCKCFGR_CK48MSEL */
644#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
645
646#if defined(RNG)
650#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
651#define LL_RCC_RNG_CLKSOURCE LL_RCC_CK48M_CLKSOURCE
652#else
653#define LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ
654#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
658#endif /* RNG */
659
660#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
664#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
665#define LL_RCC_USB_CLKSOURCE LL_RCC_CK48M_CLKSOURCE
666#else
667#define LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ
668#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
672#endif /* USB_OTG_FS || USB_OTG_HS */
673
674#if defined(CEC)
678#define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL
682#endif /* CEC */
683
687#if defined(RCC_CFGR_I2SSRC)
688#define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC
689#endif /* RCC_CFGR_I2SSRC */
690#if defined(RCC_DCKCFGR_I2SSRC)
691#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2SSRC
692#endif /* RCC_DCKCFGR_I2SSRC */
693#if defined(RCC_DCKCFGR_I2S1SRC)
694#define LL_RCC_I2S1_CLKSOURCE RCC_DCKCFGR_I2S1SRC
695#endif /* RCC_DCKCFGR_I2S1SRC */
696#if defined(RCC_DCKCFGR_I2S2SRC)
697#define LL_RCC_I2S2_CLKSOURCE RCC_DCKCFGR_I2S2SRC
698#endif /* RCC_DCKCFGR_I2S2SRC */
702
703#if defined(DFSDM1_Channel0) || defined(DFSDM2_Channel0)
707#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM1ASEL
708#if defined(DFSDM2_Channel0)
709#define LL_RCC_DFSDM2_AUDIO_CLKSOURCE RCC_DCKCFGR_CKDFSDM2ASEL
710#endif /* DFSDM2_Channel0 */
714
718#define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL
719#if defined(DFSDM2_Channel0)
720#define LL_RCC_DFSDM2_CLKSOURCE RCC_DCKCFGR_CKDFSDM1SEL
721#endif /* DFSDM2_Channel0 */
725#endif /* DFSDM1_Channel0 || DFSDM2_Channel0 */
726
727#if defined(SPDIFRX)
731#define LL_RCC_SPDIFRX1_CLKSOURCE RCC_DCKCFGR2_SPDIFRXSEL
735#endif /* SPDIFRX */
736
737#if defined(DSI)
741#define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR_DSISEL
745#endif /* DSI */
746
747#if defined(LTDC)
751#define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR
755#endif /* LTDC */
756
757
761#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U
762#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0
763#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1
764#define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL
768
769#if defined(RCC_DCKCFGR_TIMPRE)
773#define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U
774#define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE
778#endif /* RCC_DCKCFGR_TIMPRE */
779
783#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
784#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
785#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
786#define LL_RCC_PLLI2SSOURCE_PIN (RCC_PLLI2SCFGR_PLLI2SSRC | 0x80U)
787#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
791
795#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1)
796#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
797#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2)
798#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)
799#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)
800#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
801#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3)
802#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0)
803#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1)
804#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
805#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2)
806#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)
807#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)
808#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
809#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4)
810#define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0)
811#define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1)
812#define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
813#define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2)
814#define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)
815#define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)
816#define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
817#define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3)
818#define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0)
819#define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1)
820#define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
821#define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2)
822#define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)
823#define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)
824#define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
825#define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5)
826#define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0)
827#define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1)
828#define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
829#define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2)
830#define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)
831#define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)
832#define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
833#define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3)
834#define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0)
835#define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1)
836#define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
837#define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2)
838#define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)
839#define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)
840#define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
841#define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4)
842#define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0)
843#define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1)
844#define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
845#define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2)
846#define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)
847#define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)
848#define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
849#define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3)
850#define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0)
851#define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1)
852#define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
853#define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2)
854#define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0)
855#define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1)
856#define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0)
860
861#if defined(RCC_PLLCFGR_PLLR)
865#define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1)
866#define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0)
867#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2)
868#define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0)
869#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1)
870#define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR)
874#endif /* RCC_PLLCFGR_PLLR */
875
876#if defined(RCC_DCKCFGR_PLLDIVR)
880#define LL_RCC_PLLDIVR_DIV_1 (RCC_DCKCFGR_PLLDIVR_0)
881#define LL_RCC_PLLDIVR_DIV_2 (RCC_DCKCFGR_PLLDIVR_1)
882#define LL_RCC_PLLDIVR_DIV_3 (RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)
883#define LL_RCC_PLLDIVR_DIV_4 (RCC_DCKCFGR_PLLDIVR_2)
884#define LL_RCC_PLLDIVR_DIV_5 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)
885#define LL_RCC_PLLDIVR_DIV_6 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)
886#define LL_RCC_PLLDIVR_DIV_7 (RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)
887#define LL_RCC_PLLDIVR_DIV_8 (RCC_DCKCFGR_PLLDIVR_3)
888#define LL_RCC_PLLDIVR_DIV_9 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0)
889#define LL_RCC_PLLDIVR_DIV_10 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1)
890#define LL_RCC_PLLDIVR_DIV_11 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)
891#define LL_RCC_PLLDIVR_DIV_12 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2)
892#define LL_RCC_PLLDIVR_DIV_13 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)
893#define LL_RCC_PLLDIVR_DIV_14 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)
894#define LL_RCC_PLLDIVR_DIV_15 (RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)
895#define LL_RCC_PLLDIVR_DIV_16 (RCC_DCKCFGR_PLLDIVR_4)
896#define LL_RCC_PLLDIVR_DIV_17 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_0)
897#define LL_RCC_PLLDIVR_DIV_18 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1)
898#define LL_RCC_PLLDIVR_DIV_19 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)
899#define LL_RCC_PLLDIVR_DIV_20 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2)
900#define LL_RCC_PLLDIVR_DIV_21 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)
901#define LL_RCC_PLLDIVR_DIV_22 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)
902#define LL_RCC_PLLDIVR_DIV_23 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)
903#define LL_RCC_PLLDIVR_DIV_24 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3)
904#define LL_RCC_PLLDIVR_DIV_25 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_0)
905#define LL_RCC_PLLDIVR_DIV_26 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1)
906#define LL_RCC_PLLDIVR_DIV_27 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)
907#define LL_RCC_PLLDIVR_DIV_28 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2)
908#define LL_RCC_PLLDIVR_DIV_29 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_0)
909#define LL_RCC_PLLDIVR_DIV_30 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1)
910#define LL_RCC_PLLDIVR_DIV_31 (RCC_DCKCFGR_PLLDIVR_4 | RCC_DCKCFGR_PLLDIVR_3 | RCC_DCKCFGR_PLLDIVR_2 | RCC_DCKCFGR_PLLDIVR_1 | RCC_DCKCFGR_PLLDIVR_0)
914#endif /* RCC_DCKCFGR_PLLDIVR */
915
919#define LL_RCC_PLLP_DIV_2 0x00000000U
920#define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0
921#define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1
922#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0)
926
930#define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1
931#define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0)
932#define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2
933#define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0)
934#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1)
935#define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0)
936#define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3
937#define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0)
938#define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1)
939#define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0)
940#define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2)
941#define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0)
942#define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1)
943#define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0)
947
951#define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U
952#define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL
956
957#if defined(RCC_PLLI2S_SUPPORT)
961#if defined(RCC_PLLI2SCFGR_PLLI2SM)
962#define LL_RCC_PLLI2SM_DIV_2 (RCC_PLLI2SCFGR_PLLI2SM_1)
963#define LL_RCC_PLLI2SM_DIV_3 (RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0)
964#define LL_RCC_PLLI2SM_DIV_4 (RCC_PLLI2SCFGR_PLLI2SM_2)
965#define LL_RCC_PLLI2SM_DIV_5 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0)
966#define LL_RCC_PLLI2SM_DIV_6 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1)
967#define LL_RCC_PLLI2SM_DIV_7 (RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0)
968#define LL_RCC_PLLI2SM_DIV_8 (RCC_PLLI2SCFGR_PLLI2SM_3)
969#define LL_RCC_PLLI2SM_DIV_9 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0)
970#define LL_RCC_PLLI2SM_DIV_10 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1)
971#define LL_RCC_PLLI2SM_DIV_11 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0)
972#define LL_RCC_PLLI2SM_DIV_12 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2)
973#define LL_RCC_PLLI2SM_DIV_13 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0)
974#define LL_RCC_PLLI2SM_DIV_14 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1)
975#define LL_RCC_PLLI2SM_DIV_15 (RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0)
976#define LL_RCC_PLLI2SM_DIV_16 (RCC_PLLI2SCFGR_PLLI2SM_4)
977#define LL_RCC_PLLI2SM_DIV_17 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0)
978#define LL_RCC_PLLI2SM_DIV_18 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1)
979#define LL_RCC_PLLI2SM_DIV_19 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0)
980#define LL_RCC_PLLI2SM_DIV_20 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2)
981#define LL_RCC_PLLI2SM_DIV_21 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0)
982#define LL_RCC_PLLI2SM_DIV_22 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1)
983#define LL_RCC_PLLI2SM_DIV_23 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0)
984#define LL_RCC_PLLI2SM_DIV_24 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3)
985#define LL_RCC_PLLI2SM_DIV_25 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0)
986#define LL_RCC_PLLI2SM_DIV_26 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1)
987#define LL_RCC_PLLI2SM_DIV_27 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0)
988#define LL_RCC_PLLI2SM_DIV_28 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2)
989#define LL_RCC_PLLI2SM_DIV_29 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0)
990#define LL_RCC_PLLI2SM_DIV_30 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1)
991#define LL_RCC_PLLI2SM_DIV_31 (RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0)
992#define LL_RCC_PLLI2SM_DIV_32 (RCC_PLLI2SCFGR_PLLI2SM_5)
993#define LL_RCC_PLLI2SM_DIV_33 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_0)
994#define LL_RCC_PLLI2SM_DIV_34 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1)
995#define LL_RCC_PLLI2SM_DIV_35 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0)
996#define LL_RCC_PLLI2SM_DIV_36 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2)
997#define LL_RCC_PLLI2SM_DIV_37 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0)
998#define LL_RCC_PLLI2SM_DIV_38 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1)
999#define LL_RCC_PLLI2SM_DIV_39 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0)
1000#define LL_RCC_PLLI2SM_DIV_40 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3)
1001#define LL_RCC_PLLI2SM_DIV_41 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0)
1002#define LL_RCC_PLLI2SM_DIV_42 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1)
1003#define LL_RCC_PLLI2SM_DIV_43 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0)
1004#define LL_RCC_PLLI2SM_DIV_44 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2)
1005#define LL_RCC_PLLI2SM_DIV_45 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0)
1006#define LL_RCC_PLLI2SM_DIV_46 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1)
1007#define LL_RCC_PLLI2SM_DIV_47 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0)
1008#define LL_RCC_PLLI2SM_DIV_48 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4)
1009#define LL_RCC_PLLI2SM_DIV_49 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_0)
1010#define LL_RCC_PLLI2SM_DIV_50 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1)
1011#define LL_RCC_PLLI2SM_DIV_51 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0)
1012#define LL_RCC_PLLI2SM_DIV_52 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2)
1013#define LL_RCC_PLLI2SM_DIV_53 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0)
1014#define LL_RCC_PLLI2SM_DIV_54 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1)
1015#define LL_RCC_PLLI2SM_DIV_55 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0)
1016#define LL_RCC_PLLI2SM_DIV_56 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3)
1017#define LL_RCC_PLLI2SM_DIV_57 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_0)
1018#define LL_RCC_PLLI2SM_DIV_58 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1)
1019#define LL_RCC_PLLI2SM_DIV_59 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0)
1020#define LL_RCC_PLLI2SM_DIV_60 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2)
1021#define LL_RCC_PLLI2SM_DIV_61 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_0)
1022#define LL_RCC_PLLI2SM_DIV_62 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1)
1023#define LL_RCC_PLLI2SM_DIV_63 (RCC_PLLI2SCFGR_PLLI2SM_5 | RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SM_3 | RCC_PLLI2SCFGR_PLLI2SM_2 | RCC_PLLI2SCFGR_PLLI2SM_1 | RCC_PLLI2SCFGR_PLLI2SM_0)
1024#else
1025#define LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2
1026#define LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3
1027#define LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4
1028#define LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5
1029#define LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6
1030#define LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7
1031#define LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8
1032#define LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9
1033#define LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10
1034#define LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11
1035#define LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12
1036#define LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13
1037#define LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14
1038#define LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15
1039#define LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16
1040#define LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17
1041#define LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18
1042#define LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19
1043#define LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20
1044#define LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21
1045#define LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22
1046#define LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23
1047#define LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24
1048#define LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25
1049#define LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26
1050#define LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27
1051#define LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28
1052#define LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29
1053#define LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30
1054#define LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31
1055#define LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32
1056#define LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33
1057#define LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34
1058#define LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35
1059#define LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36
1060#define LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37
1061#define LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38
1062#define LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39
1063#define LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40
1064#define LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41
1065#define LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42
1066#define LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43
1067#define LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44
1068#define LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45
1069#define LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46
1070#define LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47
1071#define LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48
1072#define LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49
1073#define LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50
1074#define LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51
1075#define LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52
1076#define LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53
1077#define LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54
1078#define LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55
1079#define LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56
1080#define LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57
1081#define LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58
1082#define LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59
1083#define LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60
1084#define LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61
1085#define LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62
1086#define LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63
1087#endif /* RCC_PLLI2SCFGR_PLLI2SM */
1091
1092#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
1096#define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1
1097#define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)
1098#define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2
1099#define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0)
1100#define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1)
1101#define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)
1102#define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3
1103#define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0)
1104#define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1)
1105#define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)
1106#define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2)
1107#define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0)
1108#define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1)
1109#define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0)
1113#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
1114
1115#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
1119#define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U
1120#define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0
1121#define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1
1122#define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)
1123#define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2
1124#define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)
1125#define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)
1126#define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)
1127#define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3
1128#define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0)
1129#define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1)
1130#define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)
1131#define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2)
1132#define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)
1133#define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)
1134#define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)
1135#define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4
1136#define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0)
1137#define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1)
1138#define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)
1139#define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2)
1140#define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)
1141#define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)
1142#define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)
1143#define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3)
1144#define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0)
1145#define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1)
1146#define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)
1147#define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2)
1148#define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0)
1149#define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1)
1150#define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0)
1154#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
1155
1156#if defined(RCC_DCKCFGR_PLLI2SDIVR)
1160#define LL_RCC_PLLI2SDIVR_DIV_1 (RCC_DCKCFGR_PLLI2SDIVR_0)
1161#define LL_RCC_PLLI2SDIVR_DIV_2 (RCC_DCKCFGR_PLLI2SDIVR_1)
1162#define LL_RCC_PLLI2SDIVR_DIV_3 (RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)
1163#define LL_RCC_PLLI2SDIVR_DIV_4 (RCC_DCKCFGR_PLLI2SDIVR_2)
1164#define LL_RCC_PLLI2SDIVR_DIV_5 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)
1165#define LL_RCC_PLLI2SDIVR_DIV_6 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)
1166#define LL_RCC_PLLI2SDIVR_DIV_7 (RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)
1167#define LL_RCC_PLLI2SDIVR_DIV_8 (RCC_DCKCFGR_PLLI2SDIVR_3)
1168#define LL_RCC_PLLI2SDIVR_DIV_9 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0)
1169#define LL_RCC_PLLI2SDIVR_DIV_10 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1)
1170#define LL_RCC_PLLI2SDIVR_DIV_11 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)
1171#define LL_RCC_PLLI2SDIVR_DIV_12 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2)
1172#define LL_RCC_PLLI2SDIVR_DIV_13 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)
1173#define LL_RCC_PLLI2SDIVR_DIV_14 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)
1174#define LL_RCC_PLLI2SDIVR_DIV_15 (RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)
1175#define LL_RCC_PLLI2SDIVR_DIV_16 (RCC_DCKCFGR_PLLI2SDIVR_4)
1176#define LL_RCC_PLLI2SDIVR_DIV_17 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_0)
1177#define LL_RCC_PLLI2SDIVR_DIV_18 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1)
1178#define LL_RCC_PLLI2SDIVR_DIV_19 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)
1179#define LL_RCC_PLLI2SDIVR_DIV_20 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2)
1180#define LL_RCC_PLLI2SDIVR_DIV_21 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)
1181#define LL_RCC_PLLI2SDIVR_DIV_22 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)
1182#define LL_RCC_PLLI2SDIVR_DIV_23 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)
1183#define LL_RCC_PLLI2SDIVR_DIV_24 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3)
1184#define LL_RCC_PLLI2SDIVR_DIV_25 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_0)
1185#define LL_RCC_PLLI2SDIVR_DIV_26 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1)
1186#define LL_RCC_PLLI2SDIVR_DIV_27 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)
1187#define LL_RCC_PLLI2SDIVR_DIV_28 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2)
1188#define LL_RCC_PLLI2SDIVR_DIV_29 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_0)
1189#define LL_RCC_PLLI2SDIVR_DIV_30 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1)
1190#define LL_RCC_PLLI2SDIVR_DIV_31 (RCC_DCKCFGR_PLLI2SDIVR_4 | RCC_DCKCFGR_PLLI2SDIVR_3 | RCC_DCKCFGR_PLLI2SDIVR_2 | RCC_DCKCFGR_PLLI2SDIVR_1 | RCC_DCKCFGR_PLLI2SDIVR_0)
1194#endif /* RCC_DCKCFGR_PLLI2SDIVR */
1195
1199#define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1
1200#define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0)
1201#define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2
1202#define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0)
1203#define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1)
1204#define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0)
1208
1209#if defined(RCC_PLLI2SCFGR_PLLI2SP)
1213#define LL_RCC_PLLI2SP_DIV_2 0x00000000U
1214#define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0
1215#define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1
1216#define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0)
1220#endif /* RCC_PLLI2SCFGR_PLLI2SP */
1221#endif /* RCC_PLLI2S_SUPPORT */
1222
1223#if defined(RCC_PLLSAI_SUPPORT)
1227#if defined(RCC_PLLSAICFGR_PLLSAIM)
1228#define LL_RCC_PLLSAIM_DIV_2 (RCC_PLLSAICFGR_PLLSAIM_1)
1229#define LL_RCC_PLLSAIM_DIV_3 (RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0)
1230#define LL_RCC_PLLSAIM_DIV_4 (RCC_PLLSAICFGR_PLLSAIM_2)
1231#define LL_RCC_PLLSAIM_DIV_5 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0)
1232#define LL_RCC_PLLSAIM_DIV_6 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1)
1233#define LL_RCC_PLLSAIM_DIV_7 (RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0)
1234#define LL_RCC_PLLSAIM_DIV_8 (RCC_PLLSAICFGR_PLLSAIM_3)
1235#define LL_RCC_PLLSAIM_DIV_9 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0)
1236#define LL_RCC_PLLSAIM_DIV_10 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1)
1237#define LL_RCC_PLLSAIM_DIV_11 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0)
1238#define LL_RCC_PLLSAIM_DIV_12 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2)
1239#define LL_RCC_PLLSAIM_DIV_13 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0)
1240#define LL_RCC_PLLSAIM_DIV_14 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1)
1241#define LL_RCC_PLLSAIM_DIV_15 (RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0)
1242#define LL_RCC_PLLSAIM_DIV_16 (RCC_PLLSAICFGR_PLLSAIM_4)
1243#define LL_RCC_PLLSAIM_DIV_17 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0)
1244#define LL_RCC_PLLSAIM_DIV_18 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1)
1245#define LL_RCC_PLLSAIM_DIV_19 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0)
1246#define LL_RCC_PLLSAIM_DIV_20 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2)
1247#define LL_RCC_PLLSAIM_DIV_21 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0)
1248#define LL_RCC_PLLSAIM_DIV_22 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1)
1249#define LL_RCC_PLLSAIM_DIV_23 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0)
1250#define LL_RCC_PLLSAIM_DIV_24 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3)
1251#define LL_RCC_PLLSAIM_DIV_25 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0)
1252#define LL_RCC_PLLSAIM_DIV_26 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1)
1253#define LL_RCC_PLLSAIM_DIV_27 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0)
1254#define LL_RCC_PLLSAIM_DIV_28 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2)
1255#define LL_RCC_PLLSAIM_DIV_29 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0)
1256#define LL_RCC_PLLSAIM_DIV_30 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1)
1257#define LL_RCC_PLLSAIM_DIV_31 (RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0)
1258#define LL_RCC_PLLSAIM_DIV_32 (RCC_PLLSAICFGR_PLLSAIM_5)
1259#define LL_RCC_PLLSAIM_DIV_33 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_0)
1260#define LL_RCC_PLLSAIM_DIV_34 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1)
1261#define LL_RCC_PLLSAIM_DIV_35 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0)
1262#define LL_RCC_PLLSAIM_DIV_36 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2)
1263#define LL_RCC_PLLSAIM_DIV_37 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0)
1264#define LL_RCC_PLLSAIM_DIV_38 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1)
1265#define LL_RCC_PLLSAIM_DIV_39 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0)
1266#define LL_RCC_PLLSAIM_DIV_40 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3)
1267#define LL_RCC_PLLSAIM_DIV_41 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0)
1268#define LL_RCC_PLLSAIM_DIV_42 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1)
1269#define LL_RCC_PLLSAIM_DIV_43 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0)
1270#define LL_RCC_PLLSAIM_DIV_44 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2)
1271#define LL_RCC_PLLSAIM_DIV_45 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0)
1272#define LL_RCC_PLLSAIM_DIV_46 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1)
1273#define LL_RCC_PLLSAIM_DIV_47 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0)
1274#define LL_RCC_PLLSAIM_DIV_48 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4)
1275#define LL_RCC_PLLSAIM_DIV_49 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_0)
1276#define LL_RCC_PLLSAIM_DIV_50 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1)
1277#define LL_RCC_PLLSAIM_DIV_51 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0)
1278#define LL_RCC_PLLSAIM_DIV_52 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2)
1279#define LL_RCC_PLLSAIM_DIV_53 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0)
1280#define LL_RCC_PLLSAIM_DIV_54 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1)
1281#define LL_RCC_PLLSAIM_DIV_55 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0)
1282#define LL_RCC_PLLSAIM_DIV_56 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3)
1283#define LL_RCC_PLLSAIM_DIV_57 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_0)
1284#define LL_RCC_PLLSAIM_DIV_58 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1)
1285#define LL_RCC_PLLSAIM_DIV_59 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0)
1286#define LL_RCC_PLLSAIM_DIV_60 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2)
1287#define LL_RCC_PLLSAIM_DIV_61 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_0)
1288#define LL_RCC_PLLSAIM_DIV_62 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1)
1289#define LL_RCC_PLLSAIM_DIV_63 (RCC_PLLSAICFGR_PLLSAIM_5 | RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIM_3 | RCC_PLLSAICFGR_PLLSAIM_2 | RCC_PLLSAICFGR_PLLSAIM_1 | RCC_PLLSAICFGR_PLLSAIM_0)
1290#else
1291#define LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2
1292#define LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3
1293#define LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4
1294#define LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5
1295#define LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6
1296#define LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7
1297#define LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8
1298#define LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9
1299#define LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10
1300#define LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11
1301#define LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12
1302#define LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13
1303#define LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14
1304#define LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15
1305#define LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16
1306#define LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17
1307#define LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18
1308#define LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19
1309#define LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20
1310#define LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21
1311#define LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22
1312#define LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23
1313#define LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24
1314#define LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25
1315#define LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26
1316#define LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27
1317#define LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28
1318#define LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29
1319#define LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30
1320#define LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31
1321#define LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32
1322#define LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33
1323#define LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34
1324#define LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35
1325#define LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36
1326#define LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37
1327#define LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38
1328#define LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39
1329#define LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40
1330#define LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41
1331#define LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42
1332#define LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43
1333#define LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44
1334#define LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45
1335#define LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46
1336#define LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47
1337#define LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48
1338#define LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49
1339#define LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50
1340#define LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51
1341#define LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52
1342#define LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53
1343#define LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54
1344#define LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55
1345#define LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56
1346#define LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57
1347#define LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58
1348#define LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59
1349#define LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60
1350#define LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61
1351#define LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62
1352#define LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63
1353#endif /* RCC_PLLSAICFGR_PLLSAIM */
1357
1361#define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1
1362#define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)
1363#define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2
1364#define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0)
1365#define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1)
1366#define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)
1367#define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3
1368#define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0)
1369#define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1)
1370#define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)
1371#define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2)
1372#define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0)
1373#define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1)
1374#define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0)
1378
1379#if defined(RCC_DCKCFGR_PLLSAIDIVQ)
1383#define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U
1384#define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0
1385#define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1
1386#define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)
1387#define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2
1388#define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)
1389#define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)
1390#define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)
1391#define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3
1392#define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0)
1393#define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1)
1394#define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)
1395#define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2)
1396#define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)
1397#define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)
1398#define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)
1399#define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4
1400#define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0)
1401#define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1)
1402#define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)
1403#define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2)
1404#define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)
1405#define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)
1406#define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)
1407#define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3)
1408#define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0)
1409#define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1)
1410#define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)
1411#define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2)
1412#define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0)
1413#define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1)
1414#define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0)
1418#endif /* RCC_DCKCFGR_PLLSAIDIVQ */
1419
1420#if defined(RCC_PLLSAICFGR_PLLSAIR)
1424#define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1
1425#define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0)
1426#define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2
1427#define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0)
1428#define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1)
1429#define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0)
1433#endif /* RCC_PLLSAICFGR_PLLSAIR */
1434
1435#if defined(RCC_DCKCFGR_PLLSAIDIVR)
1439#define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U
1440#define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0
1441#define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1
1442#define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0)
1446#endif /* RCC_DCKCFGR_PLLSAIDIVR */
1447
1448#if defined(RCC_PLLSAICFGR_PLLSAIP)
1452#define LL_RCC_PLLSAIP_DIV_2 0x00000000U
1453#define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0
1454#define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1
1455#define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0)
1459#endif /* RCC_PLLSAICFGR_PLLSAIP */
1460#endif /* RCC_PLLSAI_SUPPORT */
1464
1465/* Exported macro ------------------------------------------------------------*/
1469
1473
1480#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1481
1487#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1491
1495
1574#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1575 ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
1576
1577#if defined(RCC_PLLR_SYSCLK_SUPPORT)
1656#define __LL_RCC_CALC_PLLRCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1657 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1658
1659#endif /* RCC_PLLR_SYSCLK_SUPPORT */
1660
1749#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1750 ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
1751
1752#if defined(DSI)
1831#define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1832 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1833#endif /* DSI */
1834
1835#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
1914#define __LL_RCC_CALC_PLLCLK_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1915 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1916#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
1917
1918#if defined(SPDIFRX)
1997#define __LL_RCC_CALC_PLLCLK_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1998 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1999#endif /* SPDIFRX */
2000
2001#if defined(RCC_PLLCFGR_PLLR)
2002#if defined(SAI1)
2115#if defined(RCC_DCKCFGR_PLLDIVR)
2116#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__, __PLLDIVR__) (((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
2117 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos )) / ((__PLLDIVR__) >> RCC_DCKCFGR_PLLDIVR_Pos ))
2118#else
2119#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
2120 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
2121#endif /* RCC_DCKCFGR_PLLDIVR */
2122#endif /* SAI1 */
2123#endif /* RCC_PLLCFGR_PLLR */
2124
2125#if defined(RCC_PLLSAI_SUPPORT)
2247#define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2248 (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos) + 1U)))
2249
2250#if defined(RCC_PLLSAICFGR_PLLSAIP)
2327#define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2328 ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) * 2U))
2329#endif /* RCC_PLLSAICFGR_PLLSAIP */
2330
2331#if defined(LTDC)
2417#define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
2418 (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR_PLLSAIDIVR_Pos])))
2419#endif /* LTDC */
2420#endif /* RCC_PLLSAI_SUPPORT */
2421
2422#if defined(RCC_PLLI2S_SUPPORT)
2423#if defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR)
2586#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
2587#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2588 (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos) + 1U)))
2589#else
2590#define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2591 (((__PLLI2SQ_R__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos) * ((__PLLI2SDIVQ_R__) >> RCC_DCKCFGR_PLLI2SDIVR_Pos)))
2592
2593#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
2594#endif /* RCC_DCKCFGR_PLLI2SDIVQ || RCC_DCKCFGR_PLLI2SDIVR */
2595
2596#if defined(SPDIFRX)
2673#define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2674 ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
2675
2676#endif /* SPDIFRX */
2677
2758#define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2759 ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
2760
2761#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
2848#define __LL_RCC_CALC_PLLI2S_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
2849 ((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos))
2850
2851#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
2852#endif /* RCC_PLLI2S_SUPPORT */
2853
2869#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) &\
2870 RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
2871
2883#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
2884
2896#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
2897
2901
2905
2906/* Exported functions --------------------------------------------------------*/
2910
2914
2920__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
2921{
2922 SET_BIT(RCC->CR, RCC_CR_CSSON);
2923}
2924
2930__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
2931{
2932 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
2933}
2934
2940__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
2941{
2942 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
2943}
2944
2950__STATIC_INLINE void LL_RCC_HSE_Enable(void)
2951{
2952 SET_BIT(RCC->CR, RCC_CR_HSEON);
2953}
2954
2960__STATIC_INLINE void LL_RCC_HSE_Disable(void)
2961{
2962 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
2963}
2964
2970__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
2971{
2972 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
2973}
2974
2978
2982
2988__STATIC_INLINE void LL_RCC_HSI_Enable(void)
2989{
2990 SET_BIT(RCC->CR, RCC_CR_HSION);
2991}
2992
2998__STATIC_INLINE void LL_RCC_HSI_Disable(void)
2999{
3000 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
3001}
3002
3008__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
3009{
3010 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
3011}
3012
3020__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
3021{
3022 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
3023}
3024
3034__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
3035{
3036 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
3037}
3038
3044__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
3045{
3046 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
3047}
3048
3052
3056
3062__STATIC_INLINE void LL_RCC_LSE_Enable(void)
3063{
3064 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
3065}
3066
3072__STATIC_INLINE void LL_RCC_LSE_Disable(void)
3073{
3074 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
3075}
3076
3082__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
3083{
3084 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
3085}
3086
3092__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
3093{
3094 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
3095}
3096
3102__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
3103{
3104 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
3105}
3106
3107#if defined(RCC_BDCR_LSEMOD)
3114__STATIC_INLINE void LL_RCC_LSE_EnableHighDriveMode(void)
3115{
3116 SET_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
3117}
3118
3125__STATIC_INLINE void LL_RCC_LSE_DisableHighDriveMode(void)
3126{
3127 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEMOD);
3128}
3129#endif /* RCC_BDCR_LSEMOD */
3130
3134
3138
3144__STATIC_INLINE void LL_RCC_LSI_Enable(void)
3145{
3146 SET_BIT(RCC->CSR, RCC_CSR_LSION);
3147}
3148
3154__STATIC_INLINE void LL_RCC_LSI_Disable(void)
3155{
3156 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
3157}
3158
3164__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
3165{
3166 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
3167}
3168
3172
3176
3189__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
3190{
3191 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
3192}
3193
3205__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
3206{
3207 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
3208}
3209
3225__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
3226{
3227 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
3228}
3229
3241__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
3242{
3243 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
3244}
3245
3257__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
3258{
3259 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
3260}
3261
3276__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
3277{
3278 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
3279}
3280
3291__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
3292{
3293 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
3294}
3295
3306__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
3307{
3308 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
3309}
3310
3314
3318
3319#if defined(RCC_CFGR_MCO1EN)
3325__STATIC_INLINE void LL_RCC_MCO1_Enable(void)
3326{
3327 SET_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
3328}
3329
3335__STATIC_INLINE void LL_RCC_MCO1_Disable(void)
3336{
3337 CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO1EN);
3338}
3339#endif /* RCC_CFGR_MCO1EN */
3340
3341#if defined(RCC_CFGR_MCO2EN)
3347__STATIC_INLINE void LL_RCC_MCO2_Enable(void)
3348{
3349 SET_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
3350}
3351
3357__STATIC_INLINE void LL_RCC_MCO2_Disable(void)
3358{
3359 CLEAR_BIT(RCC->CFGR, RCC_CFGR_MCO2EN);
3360}
3361#endif /* RCC_CFGR_MCO2EN */
3362
3391__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
3392{
3393 MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U));
3394}
3395
3399
3403#if defined(FMPI2C1)
3413__STATIC_INLINE void LL_RCC_SetFMPI2CClockSource(uint32_t FMPI2CxSource)
3414{
3415 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, FMPI2CxSource);
3416}
3417#endif /* FMPI2C1 */
3418
3419#if defined(LPTIM1)
3430__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
3431{
3432 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
3433}
3434#endif /* LPTIM1 */
3435
3436#if defined(SAI1)
3466__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
3467{
3468 MODIFY_REG(RCC->DCKCFGR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
3469}
3470#endif /* SAI1 */
3471
3472#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
3482__STATIC_INLINE void LL_RCC_SetSDIOClockSource(uint32_t SDIOxSource)
3483{
3484#if defined(RCC_DCKCFGR_SDIOSEL)
3485 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL, SDIOxSource);
3486#else
3487 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, SDIOxSource);
3488#endif /* RCC_DCKCFGR_SDIOSEL */
3489}
3490#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
3491
3492#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
3505__STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
3506{
3507#if defined(RCC_DCKCFGR_CK48MSEL)
3508 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, CK48MxSource);
3509#else
3510 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
3511#endif /* RCC_DCKCFGR_CK48MSEL */
3512}
3513
3514#if defined(RNG)
3527__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
3528{
3529#if defined(RCC_DCKCFGR_CK48MSEL)
3530 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, RNGxSource);
3531#else
3532 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
3533#endif /* RCC_DCKCFGR_CK48MSEL */
3534}
3535#endif /* RNG */
3536
3537#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
3550__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
3551{
3552#if defined(RCC_DCKCFGR_CK48MSEL)
3553 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL, USBxSource);
3554#else
3555 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
3556#endif /* RCC_DCKCFGR_CK48MSEL */
3557}
3558#endif /* USB_OTG_FS || USB_OTG_HS */
3559#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
3560
3561#if defined(CEC)
3570__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
3571{
3572 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
3573}
3574#endif /* CEC */
3575
3595__STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
3596{
3597#if defined(RCC_CFGR_I2SSRC)
3598 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
3599#else
3600 MODIFY_REG(RCC->DCKCFGR, (Source & 0xFFFF0000U), (Source << 16U));
3601#endif /* RCC_CFGR_I2SSRC */
3602}
3603
3604#if defined(DSI)
3613__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
3614{
3615 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_DSISEL, Source);
3616}
3617#endif /* DSI */
3618
3619#if defined(DFSDM1_Channel0)
3633__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
3634{
3635 MODIFY_REG(RCC->DCKCFGR, (Source & 0x0000FFFFU), (Source >> 16U));
3636}
3637
3650__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
3651{
3652 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_CKDFSDM1SEL, Source);
3653}
3654#endif /* DFSDM1_Channel0 */
3655
3656#if defined(SPDIFRX)
3667__STATIC_INLINE void LL_RCC_SetSPDIFRXClockSource(uint32_t SPDIFRXxSource)
3668{
3669 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, SPDIFRXxSource);
3670}
3671#endif /* SPDIFRX */
3672
3673#if defined(FMPI2C1)
3684__STATIC_INLINE uint32_t LL_RCC_GetFMPI2CClockSource(uint32_t FMPI2Cx)
3685{
3686 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, FMPI2Cx));
3687}
3688#endif /* FMPI2C1 */
3689
3690#if defined(LPTIM1)
3702__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
3703{
3704 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
3705}
3706#endif /* LPTIM1 */
3707
3708#if defined(SAI1)
3744__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
3745{
3746 return (uint32_t)(READ_BIT(RCC->DCKCFGR, SAIx) >> 16U | SAIx);
3747}
3748#endif /* SAI1 */
3749
3750#if defined(RCC_DCKCFGR_SDIOSEL) || defined(RCC_DCKCFGR2_SDIOSEL)
3761__STATIC_INLINE uint32_t LL_RCC_GetSDIOClockSource(uint32_t SDIOx)
3762{
3763#if defined(RCC_DCKCFGR_SDIOSEL)
3764 return (uint32_t)(READ_BIT(RCC->DCKCFGR, SDIOx));
3765#else
3766 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDIOx));
3767#endif /* RCC_DCKCFGR_SDIOSEL */
3768}
3769#endif /* RCC_DCKCFGR_SDIOSEL || RCC_DCKCFGR2_SDIOSEL */
3770
3771#if defined(RCC_DCKCFGR_CK48MSEL) || defined(RCC_DCKCFGR2_CK48MSEL)
3785__STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
3786{
3787#if defined(RCC_DCKCFGR_CK48MSEL)
3788 return (uint32_t)(READ_BIT(RCC->DCKCFGR, CK48Mx));
3789#else
3790 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
3791#endif /* RCC_DCKCFGR_CK48MSEL */
3792}
3793
3794#if defined(RNG)
3808__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
3809{
3810#if defined(RCC_DCKCFGR_CK48MSEL)
3811 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RNGx));
3812#else
3813 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
3814#endif /* RCC_DCKCFGR_CK48MSEL */
3815}
3816#endif /* RNG */
3817
3818#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
3832__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
3833{
3834#if defined(RCC_DCKCFGR_CK48MSEL)
3835 return (uint32_t)(READ_BIT(RCC->DCKCFGR, USBx));
3836#else
3837 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
3838#endif /* RCC_DCKCFGR_CK48MSEL */
3839}
3840#endif /* USB_OTG_FS || USB_OTG_HS */
3841#endif /* RCC_DCKCFGR_CK48MSEL || RCC_DCKCFGR2_CK48MSEL */
3842
3843#if defined(CEC)
3853__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
3854{
3855 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
3856}
3857#endif /* CEC */
3858
3880__STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
3881{
3882#if defined(RCC_CFGR_I2SSRC)
3883 return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
3884#else
3885 return (uint32_t)(READ_BIT(RCC->DCKCFGR, I2Sx) >> 16U | I2Sx);
3886#endif /* RCC_CFGR_I2SSRC */
3887}
3888
3889#if defined(DFSDM1_Channel0)
3905__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
3906{
3907 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx) << 16U | DFSDMx);
3908}
3909
3924__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
3925{
3926 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DFSDMx));
3927}
3928#endif /* DFSDM1_Channel0 */
3929
3930#if defined(SPDIFRX)
3942__STATIC_INLINE uint32_t LL_RCC_GetSPDIFRXClockSource(uint32_t SPDIFRXx)
3943{
3944 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SPDIFRXx));
3945}
3946#endif /* SPDIFRX */
3947
3948#if defined(DSI)
3958__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
3959{
3960 return (uint32_t)(READ_BIT(RCC->DCKCFGR, DSIx));
3961}
3962#endif /* DSI */
3963
3967
3971
3985__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
3986{
3987 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
3988}
3989
3999__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
4000{
4001 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
4002}
4003
4009__STATIC_INLINE void LL_RCC_EnableRTC(void)
4010{
4011 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4012}
4013
4019__STATIC_INLINE void LL_RCC_DisableRTC(void)
4020{
4021 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4022}
4023
4029__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
4030{
4031 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
4032}
4033
4039__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
4040{
4041 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4042}
4043
4049__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
4050{
4051 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4052}
4053
4091__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
4092{
4093 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
4094}
4095
4132__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
4133{
4134 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
4135}
4136
4140
4141#if defined(RCC_DCKCFGR_TIMPRE)
4145
4154__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
4155{
4156 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE, Prescaler);
4157}
4158
4166__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
4167{
4168 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_TIMPRE));
4169}
4170
4174#endif /* RCC_DCKCFGR_TIMPRE */
4175
4179
4185__STATIC_INLINE void LL_RCC_PLL_Enable(void)
4186{
4187 SET_BIT(RCC->CR, RCC_CR_PLLON);
4188}
4189
4196__STATIC_INLINE void LL_RCC_PLL_Disable(void)
4197{
4198 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
4199}
4200
4206__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
4207{
4208 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
4209}
4210
4305__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R)
4306{
4307 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN,
4308 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos);
4309 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, PLLP_R);
4310#if defined(RCC_PLLR_SYSCLK_SUPPORT)
4311 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, PLLP_R);
4312#endif /* RCC_PLLR_SYSCLK_SUPPORT */
4313}
4314
4411__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
4412{
4413 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
4414 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
4415}
4416
4417#if defined(DSI)
4504__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4505{
4506 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4507 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4508}
4509#endif /* DSI */
4510
4511#if defined(RCC_PLLR_I2S_CLKSOURCE_SUPPORT)
4598__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4599{
4600 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4601 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4602}
4603#endif /* RCC_PLLR_I2S_CLKSOURCE_SUPPORT */
4604
4605#if defined(SPDIFRX)
4692__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4693{
4694 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4695 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4696}
4697#endif /* SPDIFRX */
4698
4699#if defined(RCC_PLLCFGR_PLLR)
4700#if defined(SAI1)
4822#if defined(RCC_DCKCFGR_PLLDIVR)
4823__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR,
4824 uint32_t PLLDIVR)
4825#else
4826__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4827#endif /* RCC_DCKCFGR_PLLDIVR */
4828{
4829 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
4830 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
4831#if defined(RCC_DCKCFGR_PLLDIVR)
4832 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR, PLLDIVR);
4833#endif /* RCC_DCKCFGR_PLLDIVR */
4834}
4835#endif /* SAI1 */
4836#endif /* RCC_PLLCFGR_PLLR */
4837
4846__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
4847{
4848 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
4849}
4850
4858__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
4859{
4860 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
4861}
4862
4870__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
4871{
4872 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
4873}
4874
4884__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
4885{
4886 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
4887}
4888
4909__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
4910{
4911 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
4912}
4913
4914#if defined(RCC_PLLCFGR_PLLR)
4927__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
4928{
4929 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
4930}
4931#endif /* RCC_PLLCFGR_PLLR */
4932
4933#if defined(RCC_DCKCFGR_PLLDIVR)
4971__STATIC_INLINE uint32_t LL_RCC_PLL_GetDIVR(void)
4972{
4973 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLDIVR));
4974}
4975#endif /* RCC_DCKCFGR_PLLDIVR */
4976
5044__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
5045{
5046 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
5047}
5048
5062__STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
5063{
5064 MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
5065}
5066
5072__STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
5073{
5074 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
5075}
5076
5083__STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
5084{
5085 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
5086}
5087
5096__STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
5097{
5098 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
5099}
5100
5106__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
5107{
5108 SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
5109}
5110
5116__STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
5117{
5118 CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
5119}
5120
5124
5125#if defined(RCC_PLLI2S_SUPPORT)
5129
5135__STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
5136{
5137 SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
5138}
5139
5145__STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
5146{
5147 CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
5148}
5149
5155__STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
5156{
5157 return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
5158}
5159
5160#if (defined(RCC_DCKCFGR_PLLI2SDIVQ) || defined(RCC_DCKCFGR_PLLI2SDIVR))
5339__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R,
5340 uint32_t PLLDIVQ_R)
5341{
5342 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5343 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5344#if defined(RCC_PLLI2SCFGR_PLLI2SM)
5345 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5346#else
5347 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5348#endif /* RCC_PLLI2SCFGR_PLLI2SM */
5349 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos);
5350#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
5351 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ, PLLQ_R);
5352 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, PLLDIVQ_R);
5353#else
5354 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR, PLLQ_R);
5355 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, PLLDIVQ_R);
5356#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
5357}
5358#endif /* RCC_DCKCFGR_PLLI2SDIVQ && RCC_DCKCFGR_PLLI2SDIVR */
5359
5360#if defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ)
5460__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
5461{
5462 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5463 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5464#if defined(RCC_PLLI2SCFGR_PLLI2SM)
5465 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5466#else
5467 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5468#endif /* RCC_PLLI2SCFGR_PLLI2SM */
5469 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ);
5470}
5471#endif /* RCC_PLLI2SCFGR_PLLI2SQ && !RCC_DCKCFGR_PLLI2SDIVQ */
5472
5473#if defined(SPDIFRX)
5559__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
5560{
5561 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
5562#if defined(RCC_PLLI2SCFGR_PLLI2SM)
5563 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5564#else
5565 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5566#endif /* RCC_PLLI2SCFGR_PLLI2SM */
5567 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP);
5568}
5569#endif /* SPDIFRX */
5570
5664__STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
5665{
5666 __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&RCC->PLLCFGR) + (Source & 0x80U)));
5667 MODIFY_REG(*pReg, RCC_PLLCFGR_PLLSRC, (Source & (~0x80U)));
5668#if defined(RCC_PLLI2SCFGR_PLLI2SM)
5669 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM, PLLM);
5670#else
5671 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
5672#endif /* RCC_PLLI2SCFGR_PLLI2SM */
5673 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
5674}
5675
5683__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
5684{
5685 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
5686}
5687
5688#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
5708__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
5709{
5710 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
5711}
5712#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
5713
5726__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
5727{
5728 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
5729}
5730
5731#if defined(RCC_PLLI2SCFGR_PLLI2SP)
5742__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
5743{
5744 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
5745}
5746#endif /* RCC_PLLI2SCFGR_PLLI2SP */
5747
5748#if defined(RCC_DCKCFGR_PLLI2SDIVQ)
5787__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
5788{
5789 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ));
5790}
5791#endif /* RCC_DCKCFGR_PLLI2SDIVQ */
5792
5793#if defined(RCC_DCKCFGR_PLLI2SDIVR)
5831__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVR(void)
5832{
5833 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR));
5834}
5835#endif /* RCC_DCKCFGR_PLLI2SDIVR */
5836
5905__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDivider(void)
5906{
5907#if defined(RCC_PLLI2SCFGR_PLLI2SM)
5908 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM));
5909#else
5910 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
5911#endif /* RCC_PLLI2SCFGR_PLLI2SM */
5912}
5913
5925__STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetMainSource(void)
5926{
5927#if defined(RCC_PLLI2SCFGR_PLLI2SSRC)
5928 uint32_t pllsrc = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
5929 uint32_t plli2sssrc0 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC);
5930 uint32_t plli2sssrc1 = READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SSRC) >> 15U;
5931 return (uint32_t)(pllsrc | plli2sssrc0 | plli2sssrc1);
5932#else
5933 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
5934#endif /* RCC_PLLI2SCFGR_PLLI2SSRC */
5935}
5936
5940#endif /* RCC_PLLI2S_SUPPORT */
5941
5942#if defined(RCC_PLLSAI_SUPPORT)
5946
5952__STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
5953{
5954 SET_BIT(RCC->CR, RCC_CR_PLLSAION);
5955}
5956
5962__STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
5963{
5964 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
5965}
5966
5972__STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
5973{
5974 return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
5975}
5976
6108__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ,
6109 uint32_t PLLDIVQ)
6110{
6111 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
6112#if defined(RCC_PLLSAICFGR_PLLSAIM)
6113 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
6114#else
6115 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
6116#endif /* RCC_PLLSAICFGR_PLLSAIM */
6117 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ);
6118 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, PLLDIVQ);
6119}
6120
6121#if defined(RCC_PLLSAICFGR_PLLSAIP)
6207__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
6208{
6209 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
6210#if defined(RCC_PLLSAICFGR_PLLSAIM)
6211 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM, PLLM);
6212#else
6213 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, PLLM);
6214#endif /* RCC_PLLSAICFGR_PLLSAIM */
6215 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP);
6216}
6217#endif /* RCC_PLLSAICFGR_PLLSAIP */
6218
6219#if defined(LTDC)
6314__STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR,
6315 uint32_t PLLDIVR)
6316{
6317 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
6318 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR);
6319 MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, PLLDIVR);
6320}
6321#endif /* LTDC */
6322
6391__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDivider(void)
6392{
6393#if defined(RCC_PLLSAICFGR_PLLSAIM)
6394 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM));
6395#else
6396 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
6397#endif /* RCC_PLLSAICFGR_PLLSAIM */
6398}
6399
6407__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
6408{
6409 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
6410}
6411
6431__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
6432{
6433 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
6434}
6435
6436#if defined(RCC_PLLSAICFGR_PLLSAIR)
6449__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
6450{
6451 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
6452}
6453#endif /* RCC_PLLSAICFGR_PLLSAIR */
6454
6455#if defined(RCC_PLLSAICFGR_PLLSAIP)
6466__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
6467{
6468 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
6469}
6470#endif /* RCC_PLLSAICFGR_PLLSAIP */
6471
6510__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
6511{
6512 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ));
6513}
6514
6515#if defined(RCC_DCKCFGR_PLLSAIDIVR)
6526__STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
6527{
6528 return (uint32_t)(READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR));
6529}
6530#endif /* RCC_DCKCFGR_PLLSAIDIVR */
6531
6535#endif /* RCC_PLLSAI_SUPPORT */
6536
6540
6546__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
6547{
6548 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
6549}
6550
6556__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
6557{
6558 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
6559}
6560
6566__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
6567{
6568 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
6569}
6570
6576__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
6577{
6578 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
6579}
6580
6586__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
6587{
6588 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
6589}
6590
6591#if defined(RCC_PLLI2S_SUPPORT)
6597__STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
6598{
6599 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
6600}
6601
6602#endif /* RCC_PLLI2S_SUPPORT */
6603
6604#if defined(RCC_PLLSAI_SUPPORT)
6610__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
6611{
6612 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
6613}
6614
6615#endif /* RCC_PLLSAI_SUPPORT */
6616
6622__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
6623{
6624 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
6625}
6626
6632__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
6633{
6634 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
6635}
6636
6642__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
6643{
6644 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
6645}
6646
6652__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
6653{
6654 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
6655}
6656
6662__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
6663{
6664 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
6665}
6666
6672__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
6673{
6674 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
6675}
6676
6677#if defined(RCC_PLLI2S_SUPPORT)
6683__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
6684{
6685 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
6686}
6687#endif /* RCC_PLLI2S_SUPPORT */
6688
6689#if defined(RCC_PLLSAI_SUPPORT)
6695__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
6696{
6697 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
6698}
6699#endif /* RCC_PLLSAI_SUPPORT */
6700
6706__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
6707{
6708 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
6709}
6710
6716__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
6717{
6718 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
6719}
6720
6726__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
6727{
6728 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
6729}
6730
6736__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
6737{
6738 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
6739}
6740
6746__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
6747{
6748 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
6749}
6750
6756__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
6757{
6758 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
6759}
6760
6766__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
6767{
6768 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
6769}
6770
6771#if defined(RCC_CSR_BORRSTF)
6777__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
6778{
6779 return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
6780}
6781#endif /* RCC_CSR_BORRSTF */
6782
6788__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
6789{
6790 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
6791}
6792
6796
6800
6806__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
6807{
6808 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
6809}
6810
6816__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
6817{
6818 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
6819}
6820
6826__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
6827{
6828 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
6829}
6830
6836__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
6837{
6838 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
6839}
6840
6846__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
6847{
6848 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
6849}
6850
6851#if defined(RCC_PLLI2S_SUPPORT)
6857__STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
6858{
6859 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
6860}
6861#endif /* RCC_PLLI2S_SUPPORT */
6862
6863#if defined(RCC_PLLSAI_SUPPORT)
6869__STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
6870{
6871 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
6872}
6873#endif /* RCC_PLLSAI_SUPPORT */
6874
6880__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
6881{
6882 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
6883}
6884
6890__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
6891{
6892 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
6893}
6894
6900__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
6901{
6902 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
6903}
6904
6910__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
6911{
6912 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
6913}
6914
6920__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
6921{
6922 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
6923}
6924
6925#if defined(RCC_PLLI2S_SUPPORT)
6931__STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
6932{
6933 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
6934}
6935
6936#endif /* RCC_PLLI2S_SUPPORT */
6937
6938#if defined(RCC_PLLSAI_SUPPORT)
6944__STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
6945{
6946 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
6947}
6948#endif /* RCC_PLLSAI_SUPPORT */
6949
6955__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
6956{
6957 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
6958}
6959
6965__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
6966{
6967 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
6968}
6969
6975__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
6976{
6977 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
6978}
6979
6985__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
6986{
6987 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
6988}
6989
6995__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
6996{
6997 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
6998}
6999
7000#if defined(RCC_PLLI2S_SUPPORT)
7006__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
7007{
7008 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
7009}
7010
7011#endif /* RCC_PLLI2S_SUPPORT */
7012
7013#if defined(RCC_PLLSAI_SUPPORT)
7019__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
7020{
7021 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
7022}
7023#endif /* RCC_PLLSAI_SUPPORT */
7024
7028
7029#if defined(USE_FULL_LL_DRIVER)
7033ErrorStatus LL_RCC_DeInit(void);
7037
7041void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
7042#if defined(FMPI2C1)
7043uint32_t LL_RCC_GetFMPI2CClockFreq(uint32_t FMPI2CxSource);
7044#endif /* FMPI2C1 */
7045#if defined(LPTIM1)
7046uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
7047#endif /* LPTIM1 */
7048#if defined(SAI1)
7049uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
7050#endif /* SAI1 */
7051#if defined(SDIO)
7052uint32_t LL_RCC_GetSDIOClockFreq(uint32_t SDIOxSource);
7053#endif /* SDIO */
7054#if defined(RNG)
7055uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
7056#endif /* RNG */
7057#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
7058uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
7059#endif /* USB_OTG_FS || USB_OTG_HS */
7060#if defined(DFSDM1_Channel0)
7061uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
7062uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
7063#endif /* DFSDM1_Channel0 */
7064uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
7065#if defined(CEC)
7066uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
7067#endif /* CEC */
7068#if defined(LTDC)
7069uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
7070#endif /* LTDC */
7071#if defined(SPDIFRX)
7072uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
7073#endif /* SPDIFRX */
7074#if defined(DSI)
7075uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
7076#endif /* DSI */
7080#endif /* USE_FULL_LL_DRIVER */
7081
7085
7089
7090#endif /* defined(RCC) */
7091
7095
7096#ifdef __cplusplus
7097}
7098#endif
7099
7100#endif /* __STM32F4xx_LL_RCC_H */
7101