STM32F4xx HAL Driver master
STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_ll_pwr.h
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1
17
18/* Define to prevent recursive inclusion -------------------------------------*/
19#ifndef __STM32F4xx_LL_PWR_H
20#define __STM32F4xx_LL_PWR_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26/* Includes ------------------------------------------------------------------*/
27#include "stm32f4xx.h"
28
32
33#if defined(PWR)
34
38
39/* Private types -------------------------------------------------------------*/
40/* Private variables ---------------------------------------------------------*/
41/* Private constants ---------------------------------------------------------*/
42/* Private macros ------------------------------------------------------------*/
43/* Exported types ------------------------------------------------------------*/
44/* Exported constants --------------------------------------------------------*/
48
53#define LL_PWR_CR_CSBF PWR_CR_CSBF
54#define LL_PWR_CR_CWUF PWR_CR_CWUF
58
63#define LL_PWR_CSR_WUF PWR_CSR_WUF
64#define LL_PWR_CSR_SBF PWR_CSR_SBF
65#define LL_PWR_CSR_PVDO PWR_CSR_PVDO
66#define LL_PWR_CSR_VOS PWR_CSR_VOSRDY
67#if defined(PWR_CSR_EWUP)
68#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP
69#elif defined(PWR_CSR_EWUP1)
70#define LL_PWR_CSR_EWUP1 PWR_CSR_EWUP1
71#endif /* PWR_CSR_EWUP */
72#if defined(PWR_CSR_EWUP2)
73#define LL_PWR_CSR_EWUP2 PWR_CSR_EWUP2
74#endif /* PWR_CSR_EWUP2 */
75#if defined(PWR_CSR_EWUP3)
76#define LL_PWR_CSR_EWUP3 PWR_CSR_EWUP3
77#endif /* PWR_CSR_EWUP3 */
81
85#if defined(PWR_CR_VOS_0)
86#define LL_PWR_REGU_VOLTAGE_SCALE3 (PWR_CR_VOS_0)
87#define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR_VOS_1)
88#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS_0 | PWR_CR_VOS_1) /* The SCALE1 is not available for STM32F401xx devices */
89#else
90#define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR_VOS)
91#define LL_PWR_REGU_VOLTAGE_SCALE2 0x00000000U
92#endif /* PWR_CR_VOS_0 */
96
100#define LL_PWR_MODE_STOP_MAINREGU 0x00000000U
101#define LL_PWR_MODE_STOP_LPREGU (PWR_CR_LPDS)
102#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
103#define LL_PWR_MODE_STOP_MAINREGU_UNDERDRIVE (PWR_CR_MRUDS | PWR_CR_FPDS)
104#define LL_PWR_MODE_STOP_LPREGU_UNDERDRIVE (PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_FPDS)
105#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
106#if defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
107#define LL_PWR_MODE_STOP_MAINREGU_DEEPSLEEP (PWR_CR_MRLVDS | PWR_CR_FPDS)
108#define LL_PWR_MODE_STOP_LPREGU_DEEPSLEEP (PWR_CR_LPDS | PWR_CR_LPLVDS | PWR_CR_FPDS)
109#endif /* PWR_CR_MRLVDS && PWR_CR_LPLVDS && PWR_CR_FPDS */
110#define LL_PWR_MODE_STANDBY (PWR_CR_PDDS)
114
118#define LL_PWR_REGU_DSMODE_MAIN 0x00000000U
119#define LL_PWR_REGU_DSMODE_LOW_POWER (PWR_CR_LPDS)
123
127#define LL_PWR_PVDLEVEL_0 (PWR_CR_PLS_LEV0)
128#define LL_PWR_PVDLEVEL_1 (PWR_CR_PLS_LEV1)
129#define LL_PWR_PVDLEVEL_2 (PWR_CR_PLS_LEV2)
130#define LL_PWR_PVDLEVEL_3 (PWR_CR_PLS_LEV3)
131#define LL_PWR_PVDLEVEL_4 (PWR_CR_PLS_LEV4)
132#define LL_PWR_PVDLEVEL_5 (PWR_CR_PLS_LEV5)
133#define LL_PWR_PVDLEVEL_6 (PWR_CR_PLS_LEV6)
134#define LL_PWR_PVDLEVEL_7 (PWR_CR_PLS_LEV7)
141#if defined(PWR_CSR_EWUP)
142#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP)
143#endif /* PWR_CSR_EWUP */
144#if defined(PWR_CSR_EWUP1)
145#define LL_PWR_WAKEUP_PIN1 (PWR_CSR_EWUP1)
146#endif /* PWR_CSR_EWUP1 */
147#if defined(PWR_CSR_EWUP2)
148#define LL_PWR_WAKEUP_PIN2 (PWR_CSR_EWUP2)
149#endif /* PWR_CSR_EWUP2 */
150#if defined(PWR_CSR_EWUP3)
151#define LL_PWR_WAKEUP_PIN3 (PWR_CSR_EWUP3)
152#endif /* PWR_CSR_EWUP3 */
156
160
161
162/* Exported macro ------------------------------------------------------------*/
166
170
177#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
178
184#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
188
192
193/* Exported functions --------------------------------------------------------*/
197
201#if defined(PWR_CR_FISSR)
208__STATIC_INLINE void LL_PWR_EnableFLASHInterfaceSTOP(void)
209{
210 SET_BIT(PWR->CR, PWR_CR_FISSR);
211}
212
218__STATIC_INLINE void LL_PWR_DisableFLASHInterfaceSTOP(void)
219{
220 CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
221}
222
228__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHInterfaceSTOP(void)
229{
230 return (READ_BIT(PWR->CR, PWR_CR_FISSR) == (PWR_CR_FISSR));
231}
232#endif /* PWR_CR_FISSR */
233
234#if defined(PWR_CR_FMSSR)
241__STATIC_INLINE void LL_PWR_EnableFLASHMemorySTOP(void)
242{
243 SET_BIT(PWR->CR, PWR_CR_FMSSR);
244}
245
251__STATIC_INLINE void LL_PWR_DisableFLASHMemorySTOP(void)
252{
253 CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
254}
255
261__STATIC_INLINE uint32_t LL_PWR_IsEnabledFLASHMemorySTOP(void)
262{
263 return (READ_BIT(PWR->CR, PWR_CR_FMSSR) == (PWR_CR_FMSSR));
264}
265#endif /* PWR_CR_FMSSR */
266#if defined(PWR_CR_UDEN)
280__STATIC_INLINE void LL_PWR_EnableUnderDriveMode(void)
281{
282 SET_BIT(PWR->CR, PWR_CR_UDEN);
283}
284
290__STATIC_INLINE void LL_PWR_DisableUnderDriveMode(void)
291{
292 CLEAR_BIT(PWR->CR, PWR_CR_UDEN);
293}
294
300__STATIC_INLINE uint32_t LL_PWR_IsEnabledUnderDriveMode(void)
301{
302 return (READ_BIT(PWR->CR, PWR_CR_UDEN) == (PWR_CR_UDEN));
303}
304#endif /* PWR_CR_UDEN */
305
306#if defined(PWR_CR_ODSWEN)
312__STATIC_INLINE void LL_PWR_EnableOverDriveSwitching(void)
313{
314 SET_BIT(PWR->CR, PWR_CR_ODSWEN);
315}
316
322__STATIC_INLINE void LL_PWR_DisableOverDriveSwitching(void)
323{
324 CLEAR_BIT(PWR->CR, PWR_CR_ODSWEN);
325}
326
332__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveSwitching(void)
333{
334 return (READ_BIT(PWR->CR, PWR_CR_ODSWEN) == (PWR_CR_ODSWEN));
335}
336#endif /* PWR_CR_ODSWEN */
337#if defined(PWR_CR_ODEN)
343__STATIC_INLINE void LL_PWR_EnableOverDriveMode(void)
344{
345 SET_BIT(PWR->CR, PWR_CR_ODEN);
346}
347
353__STATIC_INLINE void LL_PWR_DisableOverDriveMode(void)
354{
355 CLEAR_BIT(PWR->CR, PWR_CR_ODEN);
356}
357
363__STATIC_INLINE uint32_t LL_PWR_IsEnabledOverDriveMode(void)
364{
365 return (READ_BIT(PWR->CR, PWR_CR_ODEN) == (PWR_CR_ODEN));
366}
367#endif /* PWR_CR_ODEN */
368#if defined(PWR_CR_MRUDS)
374__STATIC_INLINE void LL_PWR_EnableMainRegulatorDeepSleepUDMode(void)
375{
376 SET_BIT(PWR->CR, PWR_CR_MRUDS);
377}
378
384__STATIC_INLINE void LL_PWR_DisableMainRegulatorDeepSleepUDMode(void)
385{
386 CLEAR_BIT(PWR->CR, PWR_CR_MRUDS);
387}
388
394__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode(void)
395{
396 return (READ_BIT(PWR->CR, PWR_CR_MRUDS) == (PWR_CR_MRUDS));
397}
398#endif /* PWR_CR_MRUDS */
399
400#if defined(PWR_CR_LPUDS)
406__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode(void)
407{
408 SET_BIT(PWR->CR, PWR_CR_LPUDS);
409}
410
416__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode(void)
417{
418 CLEAR_BIT(PWR->CR, PWR_CR_LPUDS);
419}
420
426__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode(void)
427{
428 return (READ_BIT(PWR->CR, PWR_CR_LPUDS) == (PWR_CR_LPUDS));
429}
430#endif /* PWR_CR_LPUDS */
431
432#if defined(PWR_CR_MRLVDS)
438__STATIC_INLINE void LL_PWR_EnableMainRegulatorLowVoltageMode(void)
439{
440 SET_BIT(PWR->CR, PWR_CR_MRLVDS);
441}
442
448__STATIC_INLINE void LL_PWR_DisableMainRegulatorLowVoltageMode(void)
449{
450 CLEAR_BIT(PWR->CR, PWR_CR_MRLVDS);
451}
452
458__STATIC_INLINE uint32_t LL_PWR_IsEnabledMainRegulatorLowVoltageMode(void)
459{
460 return (READ_BIT(PWR->CR, PWR_CR_MRLVDS) == (PWR_CR_MRLVDS));
461}
462#endif /* PWR_CR_MRLVDS */
463
464#if defined(PWR_CR_LPLVDS)
470__STATIC_INLINE void LL_PWR_EnableLowPowerRegulatorLowVoltageMode(void)
471{
472 SET_BIT(PWR->CR, PWR_CR_LPLVDS);
473}
474
480__STATIC_INLINE void LL_PWR_DisableLowPowerRegulatorLowVoltageMode(void)
481{
482 CLEAR_BIT(PWR->CR, PWR_CR_LPLVDS);
483}
484
490__STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRegulatorLowVoltageMode(void)
491{
492 return (READ_BIT(PWR->CR, PWR_CR_LPLVDS) == (PWR_CR_LPLVDS));
493}
494#endif /* PWR_CR_LPLVDS */
505__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
506{
507 MODIFY_REG(PWR->CR, PWR_CR_VOS, VoltageScaling);
508}
509
519__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
520{
521 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_VOS));
522}
528__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
529{
530 SET_BIT(PWR->CR, PWR_CR_FPDS);
531}
532
538__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
539{
540 CLEAR_BIT(PWR->CR, PWR_CR_FPDS);
541}
542
548__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
549{
550 return (READ_BIT(PWR->CR, PWR_CR_FPDS) == (PWR_CR_FPDS));
551}
552
558__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
559{
560 SET_BIT(PWR->CR, PWR_CR_DBP);
561}
562
568__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
569{
570 CLEAR_BIT(PWR->CR, PWR_CR_DBP);
571}
572
578__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
579{
580 return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
581}
589__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
590{
591 SET_BIT(PWR->CSR, PWR_CSR_BRE);
592}
593
601__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
602{
603 CLEAR_BIT(PWR->CSR, PWR_CSR_BRE);
604}
605
611__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
612{
613 return (READ_BIT(PWR->CSR, PWR_CSR_BRE) == (PWR_CSR_BRE));
614}
615
624__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
625{
626 MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
627}
628
636__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
637{
638 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
639}
640
663__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
664{
665#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
666 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS), PDMode);
667#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
668 MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS), PDMode);
669#else
670 MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
671#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
672}
673
695__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
696{
697#if defined(PWR_CR_MRUDS) && defined(PWR_CR_LPUDS) && defined(PWR_CR_FPDS)
698 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPUDS | PWR_CR_MRUDS)));
699#elif defined(PWR_CR_MRLVDS) && defined(PWR_CR_LPLVDS) && defined(PWR_CR_FPDS)
700 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_FPDS | PWR_CR_LPLVDS | PWR_CR_MRLVDS)));
701#else
702 return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
703#endif /* PWR_CR_MRUDS && PWR_CR_LPUDS && PWR_CR_FPDS */
704}
705
720__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
721{
722 MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
723}
724
738__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
739{
740 return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
741}
742
748__STATIC_INLINE void LL_PWR_EnablePVD(void)
749{
750 SET_BIT(PWR->CR, PWR_CR_PVDE);
751}
752
758__STATIC_INLINE void LL_PWR_DisablePVD(void)
759{
760 CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
761}
762
768__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
769{
770 return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
771}
772
787__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
788{
789 SET_BIT(PWR->CSR, WakeUpPin);
790}
791
806__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
807{
808 CLEAR_BIT(PWR->CSR, WakeUpPin);
809}
810
825__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
826{
827 return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
828}
829
830
834
838
844__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
845{
846 return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
847}
848
854__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
855{
856 return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
857}
858
864__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
865{
866 return (READ_BIT(PWR->CSR, PWR_CSR_BRR) == (PWR_CSR_BRR));
867}
873__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
874{
875 return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
876}
877
883__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
884{
885 return (READ_BIT(PWR->CSR, LL_PWR_CSR_VOS) == (LL_PWR_CSR_VOS));
886}
887#if defined(PWR_CR_ODEN)
893__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_OD(void)
894{
895 return (READ_BIT(PWR->CSR, PWR_CSR_ODRDY) == (PWR_CSR_ODRDY));
896}
897#endif /* PWR_CR_ODEN */
898
899#if defined(PWR_CR_ODSWEN)
905__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ODSW(void)
906{
907 return (READ_BIT(PWR->CSR, PWR_CSR_ODSWRDY) == (PWR_CSR_ODSWRDY));
908}
909#endif /* PWR_CR_ODSWEN */
910
911#if defined(PWR_CR_UDEN)
917__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_UD(void)
918{
919 return (READ_BIT(PWR->CSR, PWR_CSR_UDRDY) == (PWR_CSR_UDRDY));
920}
921#endif /* PWR_CR_UDEN */
927__STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
928{
929 SET_BIT(PWR->CR, PWR_CR_CSBF);
930}
931
937__STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
938{
939 SET_BIT(PWR->CR, PWR_CR_CWUF);
940}
941#if defined(PWR_CSR_UDRDY)
947__STATIC_INLINE void LL_PWR_ClearFlag_UD(void)
948{
949 WRITE_REG(PWR->CSR, PWR_CSR_UDRDY);
950}
951#endif /* PWR_CSR_UDRDY */
952
956
957#if defined(USE_FULL_LL_DRIVER)
961ErrorStatus LL_PWR_DeInit(void);
965#endif /* USE_FULL_LL_DRIVER */
966
970
974
975#endif /* defined(PWR) */
976
980
981#ifdef __cplusplus
982}
983#endif
984
985#endif /* __STM32F4xx_LL_PWR_H */