STM32F4xx HAL Driver master
STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_ll_iwdg.h
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1
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32F4xx_LL_IWDG_H
21#define STM32F4xx_LL_IWDG_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f4xx.h"
29
33
34#if defined(IWDG)
35
39
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42
43/* Private constants ---------------------------------------------------------*/
47#define LL_IWDG_KEY_RELOAD 0x0000AAAAU
48#define LL_IWDG_KEY_ENABLE 0x0000CCCCU
49#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U
50#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U
54
55/* Private macros ------------------------------------------------------------*/
56
57/* Exported types ------------------------------------------------------------*/
58/* Exported constants --------------------------------------------------------*/
62
67#define LL_IWDG_SR_PVU IWDG_SR_PVU
68#define LL_IWDG_SR_RVU IWDG_SR_RVU
72
76#define LL_IWDG_PRESCALER_4 0x00000000U
77#define LL_IWDG_PRESCALER_8 (IWDG_PR_PR_0)
78#define LL_IWDG_PRESCALER_16 (IWDG_PR_PR_1)
79#define LL_IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0)
80#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2)
81#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0)
82#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1)
86
90
91/* Exported macro ------------------------------------------------------------*/
95
99
107#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
108
115#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
119
123
124
125/* Exported functions --------------------------------------------------------*/
132
140__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)
141{
142 WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);
143}
144
151__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)
152{
153 WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);
154}
155
162__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)
163{
164 WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);
165}
166
173__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)
174{
175 WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);
176}
177
192__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)
193{
194 WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);
195}
196
210__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx)
211{
212 return (READ_REG(IWDGx->PR));
213}
214
222__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)
223{
224 WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);
225}
226
233__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx)
234{
235 return (READ_REG(IWDGx->RLR));
236}
237
241
245
252__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx)
253{
254 return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);
255}
256
263__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx)
264{
265 return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);
266}
267
275__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx)
276{
277 return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U) ? 1UL : 0UL);
278}
279
283
287
291
292#endif /* IWDG */
293
297
298#ifdef __cplusplus
299}
300#endif
301
302#endif /* STM32F4xx_LL_IWDG_H */