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STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_ll_i2c.h
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1
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef __STM32F4xx_LL_I2C_H
21#define __STM32F4xx_LL_I2C_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f4xx.h"
29
33
34#if defined (I2C1) || defined (I2C2) || defined (I2C3)
35
39
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42
43/* Private constants ---------------------------------------------------------*/
47
48/* Defines used to perform compute and check in the macros */
49#define LL_I2C_MAX_SPEED_STANDARD 100000U
50#define LL_I2C_MAX_SPEED_FAST 400000U
54
55/* Private macros ------------------------------------------------------------*/
56#if defined(USE_FULL_LL_DRIVER)
63#endif /*USE_FULL_LL_DRIVER*/
64
65/* Exported types ------------------------------------------------------------*/
66#if defined(USE_FULL_LL_DRIVER)
70typedef struct
71{
72 uint32_t PeripheralMode;
76
77 uint32_t ClockSpeed;
82
83 uint32_t DutyCycle;
87
88#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
89 uint32_t AnalogFilter;
93
94 uint32_t DigitalFilter;
98
99#endif
100 uint32_t OwnAddress1;
104
105 uint32_t TypeAcknowledge;
109
110 uint32_t OwnAddrSize;
114} LL_I2C_InitTypeDef;
118#endif /*USE_FULL_LL_DRIVER*/
119
120/* Exported constants --------------------------------------------------------*/
124
129#define LL_I2C_SR1_SB I2C_SR1_SB
130#define LL_I2C_SR1_ADDR I2C_SR1_ADDR
132#define LL_I2C_SR1_BTF I2C_SR1_BTF
133#define LL_I2C_SR1_ADD10 I2C_SR1_ADD10
134#define LL_I2C_SR1_STOPF I2C_SR1_STOPF
135#define LL_I2C_SR1_RXNE I2C_SR1_RXNE
136#define LL_I2C_SR1_TXE I2C_SR1_TXE
137#define LL_I2C_SR1_BERR I2C_SR1_BERR
138#define LL_I2C_SR1_ARLO I2C_SR1_ARLO
139#define LL_I2C_SR1_AF I2C_SR1_AF
140#define LL_I2C_SR1_OVR I2C_SR1_OVR
141#define LL_I2C_SR1_PECERR I2C_ISR_PECERR
142#define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT
143#define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT
144#define LL_I2C_SR2_MSL I2C_SR2_MSL
145#define LL_I2C_SR2_BUSY I2C_SR2_BUSY
146#define LL_I2C_SR2_TRA I2C_SR2_TRA
147#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL
148#define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT
149#define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST
150#define LL_I2C_SR2_DUALF I2C_SR2_DUALF
154
159#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN
160#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN
161#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN
165
166#if defined(I2C_FLTR_ANOFF)
170#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U
171#define LL_I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF
175
176#endif
180#define LL_I2C_OWNADDRESS1_7BIT 0x00004000U
181#define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U)
185
189#define LL_I2C_DUTYCYCLE_2 0x00000000U
190#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY
194
198#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U
199#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS
203
207#define LL_I2C_MODE_I2C 0x00000000U
208#define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP)
209#define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS
210#define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP)
214
218#define LL_I2C_ACK I2C_CR1_ACK
219#define LL_I2C_NACK 0x00000000U
223
227#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA
228#define LL_I2C_DIRECTION_READ 0x00000000U
232
236
237/* Exported macro ------------------------------------------------------------*/
241
245
253#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
254
261#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
265
269
275#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U)
276
282#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U)
283
290#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U))
291
301#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \
302 (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \
303 (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__))))
304
311#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U)))
312
322#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \
323 (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \
324 (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U))))
325
331#define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
332
338#define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
339
345#define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
346
350
354
355/* Exported functions --------------------------------------------------------*/
356
360
364
371__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
372{
373 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
374}
375
382__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
383{
384 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
385}
386
393__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
394{
395 return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
396}
397
398#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
413__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
414{
415 MODIFY_REG(I2Cx->FLTR, I2C_FLTR_ANOFF | I2C_FLTR_DNF, AnalogFilter | DigitalFilter);
416}
417#endif
418#if defined(I2C_FLTR_DNF)
419
430__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
431{
432 MODIFY_REG(I2Cx->FLTR, I2C_FLTR_DNF, DigitalFilter);
433}
434
441__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
442{
443 return (uint32_t)(READ_BIT(I2Cx->FLTR, I2C_FLTR_DNF));
444}
445#endif
446#if defined(I2C_FLTR_ANOFF)
447
455__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
456{
457 CLEAR_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
458}
459
467__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
468{
469 SET_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF);
470}
471
478__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
479{
480 return (READ_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF) == (I2C_FLTR_ANOFF));
481}
482#endif
483
490__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
491{
492 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
493}
494
501__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
502{
503 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
504}
505
512__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
513{
514 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
515}
516
523__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
524{
525 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
526}
527
534__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
535{
536 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN);
537}
538
545__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
546{
547 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN));
548}
549
556__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx)
557{
558 return (uint32_t) & (I2Cx->DR);
559}
560
568__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
569{
570 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
571}
572
580__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
581{
582 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
583}
584
591__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
592{
593 return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
594}
595
603__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
604{
605 SET_BIT(I2Cx->CR1, I2C_CR1_ENGC);
606}
607
615__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
616{
617 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC);
618}
619
626__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
627{
628 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC));
629}
630
644__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
645{
646 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize);
647}
648
657__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2)
658{
659 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2);
660}
661
668__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
669{
670 SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
671}
672
679__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
680{
681 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL);
682}
683
690__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
691{
692 return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL));
693}
694
702__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock)
703{
704 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock));
705}
706
713__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx)
714{
715 return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ)));
716}
717
727__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle)
728{
729 MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle);
730}
731
740__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx)
741{
742 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY));
743}
744
754__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode)
755{
756 MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode);
757}
758
767__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx)
768{
769 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS));
770}
771
780__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime)
781{
782 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime);
783}
784
791__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx)
792{
793 return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE));
794}
795
804__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod)
805{
806 MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod);
807}
808
815__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx)
816{
817 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR));
818}
819
836__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed,
837 uint32_t DutyCycle)
838{
839 uint32_t freqrange = 0x0U;
840 uint32_t clockconfig = 0x0U;
841
842 /* Compute frequency range */
843 freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock);
844
845 /* Configure I2Cx: Frequency range register */
846 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange);
847
848 /* Configure I2Cx: Rise Time register */
849 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed));
850
851 /* Configure Speed mode, Duty Cycle and Clock control register value */
852 if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD)
853 {
854 /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */
855 clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \
856 __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \
857 DutyCycle;
858 }
859 else
860 {
861 /* Set Speed mode at standard for Clock Speed request in standard clock range */
862 clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \
863 __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed);
864 }
865
866 /* Configure I2Cx: Clock control register */
867 MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig);
868}
869
885__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
886{
887 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode);
888}
889
904__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
905{
906 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP));
907}
908
922__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
923{
924 SET_BIT(I2Cx->CR1, I2C_CR1_ALERT);
925}
926
940__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
941{
942 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT);
943}
944
953__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
954{
955 return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT));
956}
957
966__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
967{
968 SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
969}
970
979__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
980{
981 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC);
982}
983
992__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
993{
994 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC));
995}
996
1000
1004
1012__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
1013{
1014 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
1015}
1016
1024__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
1025{
1026 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
1027}
1028
1036__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
1037{
1038 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
1039}
1040
1048__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
1049{
1050 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
1051}
1052
1060__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
1061{
1062 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN);
1063}
1064
1072__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
1073{
1074 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN));
1075}
1076
1093__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx)
1094{
1095 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
1096}
1097
1112__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx)
1113{
1114 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN);
1115}
1116
1123__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx)
1124{
1125 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN));
1126}
1127
1137__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx)
1138{
1139 SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
1140}
1141
1151__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx)
1152{
1153 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN);
1154}
1155
1162__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx)
1163{
1164 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN));
1165}
1166
1183__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1184{
1185 SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
1186}
1187
1204__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1205{
1206 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN);
1207}
1208
1215__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
1216{
1217 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN));
1218}
1219
1223
1227
1236__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
1237{
1238 return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE));
1239}
1240
1249__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx)
1250{
1251 return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF));
1252}
1253
1262__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
1263{
1264 return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE));
1265}
1266
1275__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx)
1276{
1277 return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB));
1278}
1279
1288__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
1289{
1290 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR));
1291}
1292
1301__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx)
1302{
1303 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10));
1304}
1305
1314__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx)
1315{
1316 return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF));
1317}
1318
1327__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
1328{
1329 return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF));
1330}
1331
1340__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
1341{
1342 return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR));
1343}
1344
1353__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
1354{
1355 return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO));
1356}
1357
1366__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
1367{
1368 return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR));
1369}
1370
1379__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1380{
1381 return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR));
1382}
1383
1392__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1393{
1394 return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT));
1395}
1396
1405__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1406{
1407 return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT));
1408}
1409
1418__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
1419{
1420 return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY));
1421}
1422
1431__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx)
1432{
1433 return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF));
1434}
1435
1447__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx)
1448{
1449 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST));
1450}
1451
1463__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx)
1464{
1465 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT));
1466}
1467
1477__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx)
1478{
1479 return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL));
1480}
1481
1490__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx)
1491{
1492 return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL));
1493}
1494
1503__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1504{
1505 __IO uint32_t tmpreg;
1506 tmpreg = I2Cx->SR1;
1507 (void) tmpreg;
1508 tmpreg = I2Cx->SR2;
1509 (void) tmpreg;
1510}
1511
1518__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx)
1519{
1520 CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF);
1521}
1522
1532__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1533{
1534 __IO uint32_t tmpreg;
1535 tmpreg = I2Cx->SR1;
1536 (void) tmpreg;
1537 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
1538}
1539
1546__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1547{
1548 CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR);
1549}
1550
1557__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1558{
1559 CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO);
1560}
1561
1568__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1569{
1570 CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR);
1571}
1572
1579__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1580{
1581 CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR);
1582}
1583
1592__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1593{
1594 CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT);
1595}
1596
1605__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1606{
1607 CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT);
1608}
1609
1613
1617
1624__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx)
1625{
1626 SET_BIT(I2Cx->CR1, I2C_CR1_SWRST);
1627}
1628
1635__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx)
1636{
1637 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST);
1638}
1639
1646__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx)
1647{
1648 return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST));
1649}
1650
1661__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
1662{
1663 MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge);
1664}
1665
1674__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
1675{
1676 SET_BIT(I2Cx->CR1, I2C_CR1_START);
1677}
1678
1685__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
1686{
1687 SET_BIT(I2Cx->CR1, I2C_CR1_STOP);
1688}
1689
1697__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx)
1698{
1699 SET_BIT(I2Cx->CR1, I2C_CR1_POS);
1700}
1701
1709__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx)
1710{
1711 CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS);
1712}
1713
1720__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx)
1721{
1722 return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS));
1723}
1724
1735__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
1736{
1737 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA));
1738}
1739
1747__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx)
1748{
1749 SET_BIT(I2Cx->CR2, I2C_CR2_LAST);
1750}
1751
1759__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx)
1760{
1761 CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST);
1762}
1763
1770__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx)
1771{
1772 return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST));
1773}
1774
1785__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
1786{
1787 SET_BIT(I2Cx->CR1, I2C_CR1_PEC);
1788}
1789
1798__STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx)
1799{
1800 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC);
1801}
1802
1811__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
1812{
1813 return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC));
1814}
1815
1824__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
1825{
1826 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos);
1827}
1828
1835__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
1836{
1837 return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR));
1838}
1839
1847__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
1848{
1849 MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data);
1850}
1851
1855
1856#if defined(USE_FULL_LL_DRIVER)
1860
1861uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
1862uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
1863void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
1864
1865
1869#endif /* USE_FULL_LL_DRIVER */
1870
1874
1878
1879#endif /* I2C1 || I2C2 || I2C3 */
1880
1884
1885#ifdef __cplusplus
1886}
1887#endif
1888
1889#endif /* __STM32F4xx_LL_I2C_H */
1890