STM32F4xx HAL Driver master
STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_ll_fsmc.c
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1
55
56/* Includes ------------------------------------------------------------------*/
57#include "stm32f4xx_hal.h"
58
62#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_PCCARD_MODULE_ENABLED) \
63 || defined(HAL_SRAM_MODULE_ENABLED)
64
69
70/* Private typedef -----------------------------------------------------------*/
71/* Private define ------------------------------------------------------------*/
72
76
77/* ----------------------- FSMC registers bit mask --------------------------- */
78
79#if defined(FSMC_Bank1)
80/* --- BCR Register ---*/
81/* BCR register clear mask */
82
83/* --- BTR Register ---*/
84/* BTR register clear mask */
85#define BTR_CLEAR_MASK ((uint32_t)(FSMC_BTR1_ADDSET | FSMC_BTR1_ADDHLD |\
86 FSMC_BTR1_DATAST | FSMC_BTR1_BUSTURN |\
87 FSMC_BTR1_CLKDIV | FSMC_BTR1_DATLAT |\
88 FSMC_BTR1_ACCMOD))
89
90/* --- BWTR Register ---*/
91/* BWTR register clear mask */
92#define BWTR_CLEAR_MASK ((uint32_t)(FSMC_BWTR1_ADDSET | FSMC_BWTR1_ADDHLD |\
93 FSMC_BWTR1_DATAST | FSMC_BWTR1_BUSTURN |\
94 FSMC_BWTR1_ACCMOD))
95#endif /* FSMC_Bank1 */
96#if defined(FSMC_Bank2_3)
97
98#if defined (FSMC_PCR_PWAITEN)
99/* --- PCR Register ---*/
100/* PCR register clear mask */
101#define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCR_PWAITEN | FSMC_PCR_PBKEN | \
102 FSMC_PCR_PTYP | FSMC_PCR_PWID | \
103 FSMC_PCR_ECCEN | FSMC_PCR_TCLR | \
104 FSMC_PCR_TAR | FSMC_PCR_ECCPS))
105/* --- PMEM Register ---*/
106/* PMEM register clear mask */
107#define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEM_MEMSET2 | FSMC_PMEM_MEMWAIT2 |\
108 FSMC_PMEM_MEMHOLD2 | FSMC_PMEM_MEMHIZ2))
109
110/* --- PATT Register ---*/
111/* PATT register clear mask */
112#define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATT_ATTSET2 | FSMC_PATT_ATTWAIT2 |\
113 FSMC_PATT_ATTHOLD2 | FSMC_PATT_ATTHIZ2))
114#else
115/* --- PCR Register ---*/
116/* PCR register clear mask */
117#define PCR_CLEAR_MASK ((uint32_t)(FSMC_PCR2_PWAITEN | FSMC_PCR2_PBKEN | \
118 FSMC_PCR2_PTYP | FSMC_PCR2_PWID | \
119 FSMC_PCR2_ECCEN | FSMC_PCR2_TCLR | \
120 FSMC_PCR2_TAR | FSMC_PCR2_ECCPS))
121/* --- PMEM Register ---*/
122/* PMEM register clear mask */
123#define PMEM_CLEAR_MASK ((uint32_t)(FSMC_PMEM2_MEMSET2 | FSMC_PMEM2_MEMWAIT2 |\
124 FSMC_PMEM2_MEMHOLD2 | FSMC_PMEM2_MEMHIZ2))
125
126/* --- PATT Register ---*/
127/* PATT register clear mask */
128#define PATT_CLEAR_MASK ((uint32_t)(FSMC_PATT2_ATTSET2 | FSMC_PATT2_ATTWAIT2 |\
129 FSMC_PATT2_ATTHOLD2 | FSMC_PATT2_ATTHIZ2))
130
131#endif /* FSMC_PCR_PWAITEN */
132#endif /* FSMC_Bank2_3 */
133#if defined(FSMC_Bank4)
134/* --- PCR Register ---*/
135/* PCR register clear mask */
136#define PCR4_CLEAR_MASK ((uint32_t)(FSMC_PCR4_PWAITEN | FSMC_PCR4_PBKEN | \
137 FSMC_PCR4_PTYP | FSMC_PCR4_PWID | \
138 FSMC_PCR4_ECCEN | FSMC_PCR4_TCLR | \
139 FSMC_PCR4_TAR | FSMC_PCR4_ECCPS))
140/* --- PMEM Register ---*/
141/* PMEM register clear mask */
142#define PMEM4_CLEAR_MASK ((uint32_t)(FSMC_PMEM4_MEMSET4 | FSMC_PMEM4_MEMWAIT4 |\
143 FSMC_PMEM4_MEMHOLD4 | FSMC_PMEM4_MEMHIZ4))
144
145/* --- PATT Register ---*/
146/* PATT register clear mask */
147#define PATT4_CLEAR_MASK ((uint32_t)(FSMC_PATT4_ATTSET4 | FSMC_PATT4_ATTWAIT4 |\
148 FSMC_PATT4_ATTHOLD4 | FSMC_PATT4_ATTHIZ4))
149
150/* --- PIO4 Register ---*/
151/* PIO4 register clear mask */
152#define PIO4_CLEAR_MASK ((uint32_t)(FSMC_PIO4_IOSET4 | FSMC_PIO4_IOWAIT4 | \
153 FSMC_PIO4_IOHOLD4 | FSMC_PIO4_IOHIZ4))
154
155#endif /* FSMC_Bank4 */
156
160
161/* Private macro -------------------------------------------------------------*/
162/* Private variables ---------------------------------------------------------*/
163/* Private function prototypes -----------------------------------------------*/
164/* Exported functions --------------------------------------------------------*/
165
169
170#if defined(FSMC_Bank1)
171
195
212
220HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device,
221 const FSMC_NORSRAM_InitTypeDef *Init)
222{
223 uint32_t flashaccess;
224 uint32_t btcr_reg;
225 uint32_t mask;
226
227 /* Check the parameters */
228 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
229 assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
230 assert_param(IS_FSMC_MUX(Init->DataAddressMux));
231 assert_param(IS_FSMC_MEMORY(Init->MemoryType));
232 assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
233 assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
234 assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
235#if defined(FSMC_BCR1_WRAPMOD)
236 assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
237#endif /* FSMC_BCR1_WRAPMOD */
238 assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
239 assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
240 assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
241 assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
242 assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
243 assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
244#if defined(FSMC_BCR1_CCLKEN)
245 assert_param(IS_FSMC_CONTINOUS_CLOCK(Init->ContinuousClock));
246#endif /* FSMC_BCR1_CCLKEN */
247#if defined(FSMC_BCR1_WFDIS)
248 assert_param(IS_FSMC_WRITE_FIFO(Init->WriteFifo));
249#endif /* FSMC_BCR1_WFDIS */
250 assert_param(IS_FSMC_PAGESIZE(Init->PageSize));
251
252 /* Disable NORSRAM Device */
253 __FSMC_NORSRAM_DISABLE(Device, Init->NSBank);
254
255 /* Set NORSRAM device control parameters */
256 if (Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
257 {
258 flashaccess = FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
259 }
260 else
261 {
262 flashaccess = FSMC_NORSRAM_FLASH_ACCESS_DISABLE;
263 }
264
265 btcr_reg = (flashaccess | \
266 Init->DataAddressMux | \
267 Init->MemoryType | \
268 Init->MemoryDataWidth | \
269 Init->BurstAccessMode | \
270 Init->WaitSignalPolarity | \
271 Init->WaitSignalActive | \
272 Init->WriteOperation | \
273 Init->WaitSignal | \
274 Init->ExtendedMode | \
275 Init->AsynchronousWait | \
276 Init->WriteBurst);
277
278#if defined(FSMC_BCR1_WRAPMOD)
279 btcr_reg |= Init->WrapMode;
280#endif /* FSMC_BCR1_WRAPMOD */
281#if defined(FSMC_BCR1_CCLKEN)
282 btcr_reg |= Init->ContinuousClock;
283#endif /* FSMC_BCR1_CCLKEN */
284#if defined(FSMC_BCR1_WFDIS)
285 btcr_reg |= Init->WriteFifo;
286#endif /* FSMC_BCR1_WFDIS */
287 btcr_reg |= Init->PageSize;
288
289 mask = (FSMC_BCR1_MBKEN |
290 FSMC_BCR1_MUXEN |
291 FSMC_BCR1_MTYP |
292 FSMC_BCR1_MWID |
293 FSMC_BCR1_FACCEN |
294 FSMC_BCR1_BURSTEN |
295 FSMC_BCR1_WAITPOL |
296 FSMC_BCR1_WAITCFG |
297 FSMC_BCR1_WREN |
298 FSMC_BCR1_WAITEN |
299 FSMC_BCR1_EXTMOD |
300 FSMC_BCR1_ASYNCWAIT |
301 FSMC_BCR1_CBURSTRW);
302
303#if defined(FSMC_BCR1_WRAPMOD)
304 mask |= FSMC_BCR1_WRAPMOD;
305#endif /* FSMC_BCR1_WRAPMOD */
306#if defined(FSMC_BCR1_CCLKEN)
307 mask |= FSMC_BCR1_CCLKEN;
308#endif /* FSMC_BCR1_CCLKEN */
309#if defined(FSMC_BCR1_WFDIS)
310 mask |= FSMC_BCR1_WFDIS;
311#endif /* FSMC_BCR1_WFDIS */
312 mask |= FSMC_BCR1_CPSIZE;
313
314 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);
315
316#if defined(FSMC_BCR1_CCLKEN)
317 /* Configure synchronous mode when Continuous clock is enabled for bank2..4 */
318 if ((Init->ContinuousClock == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FSMC_NORSRAM_BANK1))
319 {
320 MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN, Init->ContinuousClock);
321 }
322#endif /* FSMC_BCR1_CCLKEN */
323#if defined(FSMC_BCR1_WFDIS)
324
325 if (Init->NSBank != FSMC_NORSRAM_BANK1)
326 {
327 /* Configure Write FIFO mode when Write Fifo is enabled for bank2..4 */
328 SET_BIT(Device->BTCR[FSMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));
329 }
330#endif /* FSMC_BCR1_WFDIS */
331
332 return HAL_OK;
333}
334
342HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device,
343 FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
344{
345 /* Check the parameters */
346 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
347 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
348 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
349
350 /* Disable the FSMC_NORSRAM device */
351 __FSMC_NORSRAM_DISABLE(Device, Bank);
352
353 /* De-initialize the FSMC_NORSRAM device */
354 /* FSMC_NORSRAM_BANK1 */
355 if (Bank == FSMC_NORSRAM_BANK1)
356 {
357 Device->BTCR[Bank] = 0x000030DBU;
358 }
359 /* FSMC_NORSRAM_BANK2, FSMC_NORSRAM_BANK3 or FSMC_NORSRAM_BANK4 */
360 else
361 {
362 Device->BTCR[Bank] = 0x000030D2U;
363 }
364
365 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;
366 ExDevice->BWTR[Bank] = 0x0FFFFFFFU;
367
368 return HAL_OK;
369}
370
379HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device,
380 const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
381{
382#if defined(FSMC_BCR1_CCLKEN)
383 uint32_t tmpr;
384#endif /* FSMC_BCR1_CCLKEN */
385
386 /* Check the parameters */
387 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
388 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
389 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
390 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
391 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
392 assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
393 assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
394 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
395 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
396
397 /* Set FSMC_NORSRAM device timing parameters */
398 Device->BTCR[Bank + 1U] =
399 (Timing->AddressSetupTime << FSMC_BTR1_ADDSET_Pos) |
400 (Timing->AddressHoldTime << FSMC_BTR1_ADDHLD_Pos) |
401 (Timing->DataSetupTime << FSMC_BTR1_DATAST_Pos) |
402 (Timing->BusTurnAroundDuration << FSMC_BTR1_BUSTURN_Pos) |
403 ((Timing->CLKDivision - 1U) << FSMC_BTR1_CLKDIV_Pos) |
404 ((Timing->DataLatency - 2U) << FSMC_BTR1_DATLAT_Pos) |
405 Timing->AccessMode;
406
407#if defined(FSMC_BCR1_CCLKEN)
408 /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */
409 if (HAL_IS_BIT_SET(Device->BTCR[FSMC_NORSRAM_BANK1], FSMC_BCR1_CCLKEN))
410 {
411 tmpr = (uint32_t)(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FSMC_BTR1_CLKDIV_Pos));
412 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FSMC_BTR1_CLKDIV_Pos);
413 MODIFY_REG(Device->BTCR[FSMC_NORSRAM_BANK1 + 1U], FSMC_BTR1_CLKDIV, tmpr);
414 }
415
416#endif /* FSMC_BCR1_CCLKEN */
417 return HAL_OK;
418}
419
432HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device,
433 const FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank,
434 uint32_t ExtendedMode)
435{
436 /* Check the parameters */
437 assert_param(IS_FSMC_EXTENDED_MODE(ExtendedMode));
438
439 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
440 if (ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
441 {
442 /* Check the parameters */
443 assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(Device));
444 assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
445 assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
446 assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
447 assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
448 assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
449 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
450
451 /* Set NORSRAM device timing register for write configuration, if extended mode is used */
452 MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime |
453 ((Timing->AddressHoldTime) << FSMC_BWTR1_ADDHLD_Pos) |
454 ((Timing->DataSetupTime) << FSMC_BWTR1_DATAST_Pos) |
455 Timing->AccessMode |
456 ((Timing->BusTurnAroundDuration) << FSMC_BWTR1_BUSTURN_Pos)));
457 }
458 else
459 {
460 Device->BWTR[Bank] = 0x0FFFFFFFU;
461 }
462
463 return HAL_OK;
464}
468
483
490HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
491{
492 /* Check the parameters */
493 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
494 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
495
496 /* Enable write operation */
497 SET_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
498
499 return HAL_OK;
500}
501
508HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
509{
510 /* Check the parameters */
511 assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
512 assert_param(IS_FSMC_NORSRAM_BANK(Bank));
513
514 /* Disable write operation */
515 CLEAR_BIT(Device->BTCR[Bank], FSMC_WRITE_OPERATION_ENABLE);
516
517 return HAL_OK;
518}
519
523
527#endif /* FSMC_Bank1 */
528
529#if defined(FSMC_Bank2_3)
530
555
572
580HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, const FSMC_NAND_InitTypeDef *Init)
581{
582 /* Check the parameters */
583 assert_param(IS_FSMC_NAND_DEVICE(Device));
584 assert_param(IS_FSMC_NAND_BANK(Init->NandBank));
585 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
586 assert_param(IS_FSMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth));
587 assert_param(IS_FSMC_ECC_STATE(Init->EccComputation));
588 assert_param(IS_FSMC_ECCPAGE_SIZE(Init->ECCPageSize));
589 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
590 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
591
592 /* Set NAND device control parameters */
593 if (Init->NandBank == FSMC_NAND_BANK2)
594 {
595 /* NAND bank 2 registers configuration */
596 MODIFY_REG(Device->PCR2, PCR_CLEAR_MASK, (Init->Waitfeature |
597 FSMC_PCR_MEMORY_TYPE_NAND |
598 Init->MemoryDataWidth |
599 Init->EccComputation |
600 Init->ECCPageSize |
601 ((Init->TCLRSetupTime) << FSMC_PCR2_TCLR_Pos) |
602 ((Init->TARSetupTime) << FSMC_PCR2_TAR_Pos)));
603 }
604 else
605 {
606 /* NAND bank 3 registers configuration */
607 MODIFY_REG(Device->PCR3, PCR_CLEAR_MASK, (Init->Waitfeature |
608 FSMC_PCR_MEMORY_TYPE_NAND |
609 Init->MemoryDataWidth |
610 Init->EccComputation |
611 Init->ECCPageSize |
612 ((Init->TCLRSetupTime) << FSMC_PCR2_TCLR_Pos) |
613 ((Init->TARSetupTime) << FSMC_PCR2_TAR_Pos)));
614 }
615
616 return HAL_OK;
617}
618
627HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
628 const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
629{
630 /* Check the parameters */
631 assert_param(IS_FSMC_NAND_DEVICE(Device));
632 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
633 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
634 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
635 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
636 assert_param(IS_FSMC_NAND_BANK(Bank));
637
638 /* Set FSMC_NAND device timing parameters */
639 if (Bank == FSMC_NAND_BANK2)
640 {
641 /* NAND bank 2 registers configuration */
642 WRITE_REG(Device->PMEM2, (Timing->SetupTime |
643 ((Timing->WaitSetupTime) << FSMC_PMEM2_MEMWAIT2_Pos) |
644 ((Timing->HoldSetupTime) << FSMC_PMEM2_MEMHOLD2_Pos) |
645 ((Timing->HiZSetupTime) << FSMC_PMEM2_MEMHIZ2_Pos)));
646 }
647 else
648 {
649 /* NAND bank 3 registers configuration */
650 WRITE_REG(Device->PMEM3, (Timing->SetupTime |
651 ((Timing->WaitSetupTime) << FSMC_PMEM2_MEMWAIT2_Pos) |
652 ((Timing->HoldSetupTime) << FSMC_PMEM2_MEMHOLD2_Pos) |
653 ((Timing->HiZSetupTime) << FSMC_PMEM2_MEMHIZ2_Pos)));
654 }
655
656 return HAL_OK;
657}
658
667HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device,
668 const FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
669{
670 /* Check the parameters */
671 assert_param(IS_FSMC_NAND_DEVICE(Device));
672 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
673 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
674 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
675 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
676 assert_param(IS_FSMC_NAND_BANK(Bank));
677
678 /* Set FSMC_NAND device timing parameters */
679 if (Bank == FSMC_NAND_BANK2)
680 {
681 /* NAND bank 2 registers configuration */
682 WRITE_REG(Device->PATT2, (Timing->SetupTime |
683 ((Timing->WaitSetupTime) << FSMC_PATT2_ATTWAIT2_Pos) |
684 ((Timing->HoldSetupTime) << FSMC_PATT2_ATTHOLD2_Pos) |
685 ((Timing->HiZSetupTime) << FSMC_PATT2_ATTHIZ2_Pos)));
686 }
687 else
688 {
689 /* NAND bank 3 registers configuration */
690 WRITE_REG(Device->PATT3, (Timing->SetupTime |
691 ((Timing->WaitSetupTime) << FSMC_PATT2_ATTWAIT2_Pos) |
692 ((Timing->HoldSetupTime) << FSMC_PATT2_ATTHOLD2_Pos) |
693 ((Timing->HiZSetupTime) << FSMC_PATT2_ATTHIZ2_Pos)));
694 }
695
696 return HAL_OK;
697}
698
705HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
706{
707 /* Check the parameters */
708 assert_param(IS_FSMC_NAND_DEVICE(Device));
709 assert_param(IS_FSMC_NAND_BANK(Bank));
710
711 /* Disable the NAND Bank */
712 __FSMC_NAND_DISABLE(Device, Bank);
713
714 /* De-initialize the NAND Bank */
715 if (Bank == FSMC_NAND_BANK2)
716 {
717 /* Set the FSMC_NAND_BANK2 registers to their reset values */
718 WRITE_REG(Device->PCR2, 0x00000018U);
719 WRITE_REG(Device->SR2, 0x00000040U);
720 WRITE_REG(Device->PMEM2, 0xFCFCFCFCU);
721 WRITE_REG(Device->PATT2, 0xFCFCFCFCU);
722 }
723 /* FSMC_Bank3_NAND */
724 else
725 {
726 /* Set the FSMC_NAND_BANK3 registers to their reset values */
727 WRITE_REG(Device->PCR3, 0x00000018U);
728 WRITE_REG(Device->SR3, 0x00000040U);
729 WRITE_REG(Device->PMEM3, 0xFCFCFCFCU);
730 WRITE_REG(Device->PATT3, 0xFCFCFCFCU);
731 }
732
733 return HAL_OK;
734}
735
739
754
755
762HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
763{
764 /* Check the parameters */
765 assert_param(IS_FSMC_NAND_DEVICE(Device));
766 assert_param(IS_FSMC_NAND_BANK(Bank));
767
768 /* Enable ECC feature */
769 if (Bank == FSMC_NAND_BANK2)
770 {
771 SET_BIT(Device->PCR2, FSMC_PCR2_ECCEN);
772 }
773 else
774 {
775 SET_BIT(Device->PCR3, FSMC_PCR2_ECCEN);
776 }
777
778 return HAL_OK;
779}
780
781
788HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
789{
790 /* Check the parameters */
791 assert_param(IS_FSMC_NAND_DEVICE(Device));
792 assert_param(IS_FSMC_NAND_BANK(Bank));
793
794 /* Disable ECC feature */
795 if (Bank == FSMC_NAND_BANK2)
796 {
797 CLEAR_BIT(Device->PCR2, FSMC_PCR2_ECCEN);
798 }
799 else
800 {
801 CLEAR_BIT(Device->PCR3, FSMC_PCR2_ECCEN);
802 }
803
804 return HAL_OK;
805}
806
815HAL_StatusTypeDef FSMC_NAND_GetECC(const FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,
816 uint32_t Timeout)
817{
818 uint32_t tickstart;
819
820 /* Check the parameters */
821 assert_param(IS_FSMC_NAND_DEVICE(Device));
822 assert_param(IS_FSMC_NAND_BANK(Bank));
823
824 /* Get tick */
825 tickstart = HAL_GetTick();
826
827 /* Wait until FIFO is empty */
828 while (__FSMC_NAND_GET_FLAG(Device, Bank, FSMC_FLAG_FEMPT) == RESET)
829 {
830 /* Check for the Timeout */
831 if (Timeout != HAL_MAX_DELAY)
832 {
833 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
834 {
835 return HAL_TIMEOUT;
836 }
837 }
838 }
839
840 if (Bank == FSMC_NAND_BANK2)
841 {
842 /* Get the ECCR2 register value */
843 *ECCval = (uint32_t)Device->ECCR2;
844 }
845 else
846 {
847 /* Get the ECCR3 register value */
848 *ECCval = (uint32_t)Device->ECCR3;
849 }
850
851 return HAL_OK;
852}
853
857#endif /* FSMC_Bank2_3 */
858
859#if defined(FSMC_Bank4)
860
883
900
908HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, const FSMC_PCCARD_InitTypeDef *Init)
909{
910 /* Check the parameters */
911 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
912#if defined(FSMC_Bank2_3)
913 assert_param(IS_FSMC_WAIT_FEATURE(Init->Waitfeature));
914 assert_param(IS_FSMC_TCLR_TIME(Init->TCLRSetupTime));
915 assert_param(IS_FSMC_TAR_TIME(Init->TARSetupTime));
916#endif /* FSMC_Bank2_3 */
917
918 /* Set FSMC_PCCARD device control parameters */
919 MODIFY_REG(Device->PCR4,
920 (FSMC_PCR4_PTYP |
921 FSMC_PCR4_PWAITEN |
922 FSMC_PCR4_PWID |
923 FSMC_PCR4_TCLR |
924 FSMC_PCR4_TAR),
925 (FSMC_PCR_MEMORY_TYPE_PCCARD |
926 Init->Waitfeature |
927 FSMC_NAND_PCC_MEM_BUS_WIDTH_16 |
928 (Init->TCLRSetupTime << FSMC_PCR4_TCLR_Pos) |
929 (Init->TARSetupTime << FSMC_PCR4_TAR_Pos)));
930
931 return HAL_OK;
932}
933
941HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
942 const FSMC_NAND_PCC_TimingTypeDef *Timing)
943{
944 /* Check the parameters */
945 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
946#if defined(FSMC_Bank2_3)
947 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
948 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
949 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
950 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
951#endif /* FSMC_Bank2_3 */
952
953 /* Set PCCARD timing parameters */
954 WRITE_REG(Device->PMEM4, (Timing->SetupTime |
955 ((Timing->WaitSetupTime) << FSMC_PMEM4_MEMWAIT4_Pos) |
956 ((Timing->HoldSetupTime) << FSMC_PMEM4_MEMHOLD4_Pos) |
957 ((Timing->HiZSetupTime) << FSMC_PMEM4_MEMHIZ4_Pos)));
958
959 return HAL_OK;
960}
961
969HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
970 const FSMC_NAND_PCC_TimingTypeDef *Timing)
971{
972 /* Check the parameters */
973 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
974#if defined(FSMC_Bank2_3)
975 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
976 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
977 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
978 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
979#endif /* FSMC_Bank2_3 */
980
981 /* Set PCCARD timing parameters */
982 WRITE_REG(Device->PATT4, (Timing->SetupTime |
983 ((Timing->WaitSetupTime) << FSMC_PATT4_ATTWAIT4_Pos) |
984 ((Timing->HoldSetupTime) << FSMC_PATT4_ATTHOLD4_Pos) |
985 ((Timing->HiZSetupTime) << FSMC_PATT4_ATTHIZ4_Pos)));
986
987 return HAL_OK;
988}
989
997HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device,
998 const FSMC_NAND_PCC_TimingTypeDef *Timing)
999{
1000 /* Check the parameters */
1001 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
1002#if defined(FSMC_Bank2_3)
1003 assert_param(IS_FSMC_SETUP_TIME(Timing->SetupTime));
1004 assert_param(IS_FSMC_WAIT_TIME(Timing->WaitSetupTime));
1005 assert_param(IS_FSMC_HOLD_TIME(Timing->HoldSetupTime));
1006 assert_param(IS_FSMC_HIZ_TIME(Timing->HiZSetupTime));
1007#endif /* FSMC_Bank2_3 */
1008
1009 /* Set FSMC_PCCARD device timing parameters */
1010 WRITE_REG(Device->PIO4, (Timing->SetupTime |
1011 (Timing->WaitSetupTime << FSMC_PIO4_IOWAIT4_Pos) |
1012 (Timing->HoldSetupTime << FSMC_PIO4_IOHOLD4_Pos) |
1013 (Timing->HiZSetupTime << FSMC_PIO4_IOHIZ4_Pos)));
1014
1015 return HAL_OK;
1016}
1017
1023HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
1024{
1025 /* Check the parameters */
1026 assert_param(IS_FSMC_PCCARD_DEVICE(Device));
1027
1028 /* Disable the FSMC_PCCARD device */
1029 __FSMC_PCCARD_DISABLE(Device);
1030
1031 /* De-initialize the FSMC_PCCARD device */
1032 Device->PCR4 = 0x00000018U;
1033 Device->SR4 = 0x00000040U;
1034 Device->PMEM4 = 0xFCFCFCFCU;
1035 Device->PATT4 = 0xFCFCFCFCU;
1036 Device->PIO4 = 0xFCFCFCFCU;
1037
1038 return HAL_OK;
1039}
1040
1044#endif /* FSMC_Bank4 */
1045
1046
1050
1054
1055#endif /* HAL_NOR_MODULE_ENABLED */
HAL_GetTick
uint32_t HAL_GetTick(void)
Provides a tick value in millisecond.
Definition stm32f4xx_hal.c:323
assert_param
#define assert_param(expr)
Definition stm32_assert_template.h:46
stm32f4xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
HAL_IS_BIT_SET
#define HAL_IS_BIT_SET(REG, BIT)
Definition stm32f4xx_hal_def.h:63
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition stm32f4xx_hal_def.h:39
HAL_TIMEOUT
@ HAL_TIMEOUT
Definition stm32f4xx_hal_def.h:43
HAL_OK
@ HAL_OK
Definition stm32f4xx_hal_def.h:40
HAL_MAX_DELAY
#define HAL_MAX_DELAY
Definition stm32f4xx_hal_def.h:61