STM32F4xx HAL Driver master
STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_ll_dac.h
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1
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32F4xx_LL_DAC_H
21#define STM32F4xx_LL_DAC_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f4xx.h"
29
33
34#if defined(DAC)
35
39
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42
43/* Private constants ---------------------------------------------------------*/
47
48/* Internal masks for DAC channels definition */
49/* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */
50/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */
51/* - channel bits position into register SWTRIG */
52/* - channel register offset of data holding register DHRx */
53/* - channel register offset of data output register DORx */
54#define DAC_CR_CH1_BITOFFSET 0UL /* Position of channel bits into registers
55 CR, MCR, CCR, SHHR, SHRR of channel 1 */
56#if defined(DAC_CHANNEL2_SUPPORT)
57#define DAC_CR_CH2_BITOFFSET 16UL /* Position of channel bits into registers
58 CR, MCR, CCR, SHHR, SHRR of channel 2 */
59#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
60#else
61#define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET)
62#endif /* DAC_CHANNEL2_SUPPORT */
63
64#define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
65#if defined(DAC_CHANNEL2_SUPPORT)
66#define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
67#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2)
68#else
69#define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1)
70#endif /* DAC_CHANNEL2_SUPPORT */
71
72#define DAC_REG_DHR12R1_REGOFFSET 0x00000000UL /* Register DHR12Rx channel 1 taken as reference */
73#define DAC_REG_DHR12L1_REGOFFSET 0x00100000UL /* Register offset of DHR12Lx channel 1 versus
74 DHR12Rx channel 1 (shifted left of 20 bits) */
75#define DAC_REG_DHR8R1_REGOFFSET 0x02000000UL /* Register offset of DHR8Rx channel 1 versus
76 DHR12Rx channel 1 (shifted left of 24 bits) */
77#if defined(DAC_CHANNEL2_SUPPORT)
78#define DAC_REG_DHR12R2_REGOFFSET 0x00030000UL /* Register offset of DHR12Rx channel 2 versus
79 DHR12Rx channel 1 (shifted left of 16 bits) */
80#define DAC_REG_DHR12L2_REGOFFSET 0x00400000UL /* Register offset of DHR12Lx channel 2 versus
81 DHR12Rx channel 1 (shifted left of 20 bits) */
82#define DAC_REG_DHR8R2_REGOFFSET 0x05000000UL /* Register offset of DHR8Rx channel 2 versus
83 DHR12Rx channel 1 (shifted left of 24 bits) */
84#endif /* DAC_CHANNEL2_SUPPORT */
85#define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000UL
86#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
87#define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000UL
88#define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK\
89 | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
90
91#define DAC_REG_DOR1_REGOFFSET 0x00000000UL /* Register DORx channel 1 taken as reference */
92#if defined(DAC_CHANNEL2_SUPPORT)
93#define DAC_REG_DOR2_REGOFFSET 0x10000000UL /* Register offset of DORx channel 1 versus
94 DORx channel 2 (shifted left of 28 bits) */
95#define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
96#endif /* DAC_CHANNEL2_SUPPORT */
97
98
99#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0 0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
100 DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
101#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of DORx registers offset when shifted
102 to position 0 */
103#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0 0x00000001UL /* Mask of SHSRx registers offset when shifted
104 to position 0 */
105
106#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS 16UL /* Position of bits register offset of DHR12Rx
107 channel 1 or 2 versus DHR12Rx channel 1
108 (shifted left of 16 bits) */
109#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS 20UL /* Position of bits register offset of DHR12Lx
110 channel 1 or 2 versus DHR12Rx channel 1
111 (shifted left of 20 bits) */
112#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS 24UL /* Position of bits register offset of DHR8Rx
113 channel 1 or 2 versus DHR12Rx channel 1
114 (shifted left of 24 bits) */
115#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS 28UL /* Position of bits register offset of DORx
116 channel 1 or 2 versus DORx channel 1
117 (shifted left of 28 bits) */
118
119/* DAC registers bits positions */
120#if defined(DAC_CHANNEL2_SUPPORT)
121#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS DAC_DHR12RD_DACC2DHR_Pos
122#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS DAC_DHR12LD_DACC2DHR_Pos
123#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS DAC_DHR8RD_DACC2DHR_Pos
124#endif /* DAC_CHANNEL2_SUPPORT */
125
126/* Miscellaneous data */
127#define DAC_DIGITAL_SCALE_12BITS 4095UL /* Full-scale digital value with a resolution of 12
128 bits (voltage range determined by analog voltage
129 references Vref+ and Vref-, refer to reference manual) */
130
134
135
136/* Private macros ------------------------------------------------------------*/
140
149#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
150 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
151
155
156
157/* Exported types ------------------------------------------------------------*/
158#if defined(USE_FULL_LL_DRIVER)
162
166typedef struct
167{
168 uint32_t TriggerSource;
175
176 uint32_t WaveAutoGeneration;
181
182 uint32_t WaveAutoGenerationConfig;
194
195 uint32_t OutputBuffer;
200} LL_DAC_InitTypeDef;
201
205#endif /* USE_FULL_LL_DRIVER */
206
207/* Exported constants --------------------------------------------------------*/
211
216/* DAC channel 1 flags */
217#define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
218#if defined(DAC_CHANNEL2_SUPPORT)
219/* DAC channel 2 flags */
220#define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
221#endif /* DAC_CHANNEL2_SUPPORT */
225
230#define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1)
231#if defined(DAC_CHANNEL2_SUPPORT)
232#define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2)
233#endif /* DAC_CHANNEL2_SUPPORT */
237
241#define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1)
242#if defined(DAC_CHANNEL2_SUPPORT)
243#define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2)
244#endif /* DAC_CHANNEL2_SUPPORT */
248
252#define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
253#define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 )
254#define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0)
255#define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0)
256#define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000UL
257#define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 )
258#define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0)
259#define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 )
263
267#define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000UL
268#define LL_DAC_WAVE_AUTO_GENERATION_NOISE ( DAC_CR_WAVE1_0)
269#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1 )
273
277#define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000UL
278#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0)
279#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 )
280#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
281#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 )
282#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
283#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
284#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
285#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 )
286#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
287#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
288#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
292
296#define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000UL
297#define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0)
298#define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 )
299#define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
300#define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 )
301#define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0)
302#define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 )
303#define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
304#define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 )
305#define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0)
306#define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 )
307#define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)
311
315#define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000UL
316#define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1)
320
324#define LL_DAC_RESOLUTION_12B 0x00000000UL
325#define LL_DAC_RESOLUTION_8B 0x00000002UL
329
333/* List of DAC registers intended to be used (most commonly) with */
334/* DMA transfer. */
335/* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */
336#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS
337#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS
338#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS
342
350
351/* Delay for DAC channel voltage settling time from DAC channel startup */
352/* (transition from disable to enable). */
353/* Note: DAC channel startup time depends on board application environment: */
354/* impedance connected to DAC channel output. */
355/* The delay below is specified under conditions: */
356/* - voltage maximum transition (lowest to highest value) */
357/* - until voltage reaches final value +-1LSB */
358/* - DAC channel output buffer enabled */
359/* - load impedance of 5kOhm (min), 50pF (max) */
360/* Literal set to maximum value (refer to device datasheet, */
361/* parameter "tWAKEUP"). */
362/* Unit: us */
363#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15UL
364
365/* Delay for DAC channel voltage settling time. */
366/* Note: DAC channel startup time depends on board application environment: */
367/* impedance connected to DAC channel output. */
368/* The delay below is specified under conditions: */
369/* - voltage maximum transition (lowest to highest value) */
370/* - until voltage reaches final value +-1LSB */
371/* - DAC channel output buffer enabled */
372/* - load impedance of 5kOhm min, 50pF max */
373/* Literal set to maximum value (refer to device datasheet, */
374/* parameter "tSETTLING"). */
375/* Unit: us */
376#define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12UL
377
381
385
386/* Exported macro ------------------------------------------------------------*/
390
394
402#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
403
410#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
411
415
419
436#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
437 ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
438
455#if defined(DAC_CHANNEL2_SUPPORT)
456#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
457 (((__DECIMAL_NB__) == 1UL) \
458 ? (LL_DAC_CHANNEL_1) \
459 : \
460 (((__DECIMAL_NB__) == 2UL) \
461 ? (LL_DAC_CHANNEL_2) \
462 : \
463 (0UL) \
464 ) \
465 )
466#else
467#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
468 (((__DECIMAL_NB__) == 1UL) \
469 ? (LL_DAC_CHANNEL_1) \
470 : \
471 (0UL) \
472 )
473#endif /* DAC_CHANNEL2_SUPPORT */
474
486#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
487 ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
488
507#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \
508 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \
509 / (__VREFANALOG_VOLTAGE__) \
510 )
511
515
519
520
521/* Exported functions --------------------------------------------------------*/
525
554__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
555{
556 MODIFY_REG(DACx->CR,
557 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
558 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
559}
560
586__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
587{
588 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
589 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
590 );
591}
592
611__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
612{
613 MODIFY_REG(DACx->CR,
614 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
615 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
616}
617
635__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
636{
637 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
638 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
639 );
640}
641
674__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
675{
676 MODIFY_REG(DACx->CR,
677 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
678 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
679}
680
707__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
708{
709 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
710 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
711 );
712}
713
746__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
747 uint32_t TriangleAmplitude)
748{
749 MODIFY_REG(DACx->CR,
750 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
751 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
752}
753
780__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
781{
782 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
783 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
784 );
785}
786
803__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
804{
805 MODIFY_REG(DACx->CR,
806 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
807 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
808}
809
825__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
826{
827 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
828 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
829 );
830}
831
835
839
855__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
856{
857 SET_BIT(DACx->CR,
858 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
859}
860
876__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
877{
878 CLEAR_BIT(DACx->CR,
879 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
880}
881
896__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
897{
898 return ((READ_BIT(DACx->CR,
899 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
900 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
901}
902
938__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
939{
940 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */
941 /* DAC channel selected. */
942 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
943 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
944}
948
952
969__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
970{
971 SET_BIT(DACx->CR,
972 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
973}
974
988__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
989{
990 CLEAR_BIT(DACx->CR,
991 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
992}
993
1008__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1009{
1010 return ((READ_BIT(DACx->CR,
1011 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1012 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1013}
1014
1036__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1037{
1038 SET_BIT(DACx->CR,
1039 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1040}
1041
1055__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1056{
1057 CLEAR_BIT(DACx->CR,
1058 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
1059}
1060
1075__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1076{
1077 return ((READ_BIT(DACx->CR,
1078 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
1079 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
1080}
1081
1106__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
1107{
1108 SET_BIT(DACx->SWTRIGR,
1109 (DAC_Channel & DAC_SWTR_CHX_MASK));
1110}
1111
1128__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1129{
1130 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
1131 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1132
1133 MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
1134}
1135
1152__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1153{
1154 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
1155 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1156
1157 MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
1158}
1159
1176__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
1177{
1178 __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
1179 & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
1180
1181 MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
1182}
1183
1184#if defined(DAC_CHANNEL2_SUPPORT)
1196__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1197 uint32_t DataChannel2)
1198{
1199 MODIFY_REG(DACx->DHR12RD,
1200 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
1201 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1202}
1203
1215__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1216 uint32_t DataChannel2)
1217{
1218 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */
1219 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */
1220 /* the 4 LSB must be taken into account for the shift value. */
1221 MODIFY_REG(DACx->DHR12LD,
1222 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
1223 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
1224}
1225
1237__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
1238 uint32_t DataChannel2)
1239{
1240 MODIFY_REG(DACx->DHR8RD,
1241 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
1242 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
1243}
1244#endif /* DAC_CHANNEL2_SUPPORT */
1245
1263__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
1264{
1265 __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
1266 & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
1267
1268 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
1269}
1270
1274
1278
1285__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
1286{
1287 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
1288}
1289
1290#if defined(DAC_CHANNEL2_SUPPORT)
1297__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
1298{
1299 return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
1300}
1301#endif /* DAC_CHANNEL2_SUPPORT */
1302
1309__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
1310{
1311 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
1312}
1313
1314#if defined(DAC_CHANNEL2_SUPPORT)
1321__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
1322{
1323 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
1324}
1325#endif /* DAC_CHANNEL2_SUPPORT */
1326
1330
1334
1341__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
1342{
1343 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1344}
1345
1346#if defined(DAC_CHANNEL2_SUPPORT)
1353__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
1354{
1355 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1356}
1357#endif /* DAC_CHANNEL2_SUPPORT */
1358
1365__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
1366{
1367 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
1368}
1369
1370#if defined(DAC_CHANNEL2_SUPPORT)
1377__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
1378{
1379 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
1380}
1381#endif /* DAC_CHANNEL2_SUPPORT */
1382
1389__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
1390{
1391 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
1392}
1393
1394#if defined(DAC_CHANNEL2_SUPPORT)
1401__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
1402{
1403 return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
1404}
1405#endif /* DAC_CHANNEL2_SUPPORT */
1406
1410
1411#if defined(USE_FULL_LL_DRIVER)
1415
1416ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
1417ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
1418void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
1419
1423#endif /* USE_FULL_LL_DRIVER */
1424
1428
1432
1433#endif /* DAC */
1434
1438
1439#ifdef __cplusplus
1440}
1441#endif
1442
1443#endif /* STM32F4xx_LL_DAC_H */