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STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_ll_adc.h
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1
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef __STM32F4xx_LL_ADC_H
21#define __STM32F4xx_LL_ADC_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f4xx.h"
29
33
34#if defined (ADC1) || defined (ADC2) || defined (ADC3)
35
39
40/* Private types -------------------------------------------------------------*/
41/* Private variables ---------------------------------------------------------*/
42
43/* Private constants ---------------------------------------------------------*/
47
48/* Internal mask for ADC group regular sequencer: */
49/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
50/* - sequencer register offset */
51/* - sequencer rank bits position into the selected register */
52
53/* Internal register offset for ADC group regular sequencer configuration */
54/* (offset placed into a spare area of literal definition) */
55#define ADC_SQR1_REGOFFSET 0x00000000UL
56#define ADC_SQR2_REGOFFSET 0x00000100UL
57#define ADC_SQR3_REGOFFSET 0x00000200UL
58#define ADC_SQR4_REGOFFSET 0x00000300UL
59
60#define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
61#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
62
63/* Definition of ADC group regular sequencer bits information to be inserted */
64/* into ADC group regular sequencer ranks literals definition. */
65#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
66#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
67#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
68#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
69#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
70#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
71#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
72#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
73#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
74#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
75#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
76#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25UL) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
77#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
78#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
79#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
80#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15UL) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
81
82/* Internal mask for ADC group injected sequencer: */
83/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
84/* - data register offset */
85/* - offset register offset */
86/* - sequencer rank bits position into the selected register */
87
88/* Internal register offset for ADC group injected data register */
89/* (offset placed into a spare area of literal definition) */
90#define ADC_JDR1_REGOFFSET 0x00000000UL
91#define ADC_JDR2_REGOFFSET 0x00000100UL
92#define ADC_JDR3_REGOFFSET 0x00000200UL
93#define ADC_JDR4_REGOFFSET 0x00000300UL
94
95/* Internal register offset for ADC group injected offset configuration */
96/* (offset placed into a spare area of literal definition) */
97#define ADC_JOFR1_REGOFFSET 0x00000000UL
98#define ADC_JOFR2_REGOFFSET 0x00001000UL
99#define ADC_JOFR3_REGOFFSET 0x00002000UL
100#define ADC_JOFR4_REGOFFSET 0x00003000UL
101
102#define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
103#define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
104#define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
105
106/* Internal mask for ADC group regular trigger: */
107/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */
108/* - regular trigger source */
109/* - regular trigger edge */
110#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
111
112/* Mask containing trigger source masks for each of possible */
113/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
114/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
115#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTSEL) >> (4UL * 0UL)) | \
116 ((ADC_CR2_EXTSEL) >> (4UL * 1UL)) | \
117 ((ADC_CR2_EXTSEL) >> (4UL * 2UL)) | \
118 ((ADC_CR2_EXTSEL) >> (4UL * 3UL)))
119
120/* Mask containing trigger edge masks for each of possible */
121/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
122/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
123#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN) >> (4UL * 0UL)) | \
124 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 1UL)) | \
125 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 2UL)) | \
126 ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 3UL)))
127
128/* Definition of ADC group regular trigger bits information. */
129#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS (24UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTSEL) */
130#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (28UL) /* Value equivalent to POSITION_VAL(ADC_CR2_EXTEN) */
131
132
133
134/* Internal mask for ADC group injected trigger: */
135/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */
136/* - injected trigger source */
137/* - injected trigger edge */
138#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT (ADC_CR2_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */
139
140/* Mask containing trigger source masks for each of possible */
141/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
142/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
143#define ADC_INJ_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_JEXTSEL) >> (4UL * 0UL)) | \
144 ((ADC_CR2_JEXTSEL) >> (4UL * 1UL)) | \
145 ((ADC_CR2_JEXTSEL) >> (4UL * 2UL)) | \
146 ((ADC_CR2_JEXTSEL) >> (4UL * 3UL)))
147
148/* Mask containing trigger edge masks for each of possible */
149/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */
150/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */
151#define ADC_INJ_TRIG_EDGE_MASK (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN) >> (4UL * 0UL)) | \
152 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 1UL)) | \
153 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 2UL)) | \
154 ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT) >> (4UL * 3UL)))
155
156/* Definition of ADC group injected trigger bits information. */
157#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS (16UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTSEL) */
158#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_CR2_JEXTEN) */
159
160/* Internal mask for ADC channel: */
161/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
162/* - channel identifier defined by number */
163/* - channel differentiation between external channels (connected to */
164/* GPIO pins) and internal channels (connected to internal paths) */
165/* - channel sampling time defined by SMPRx register offset */
166/* and SMPx bits positions into SMPRx register */
167#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
168#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0UL)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
169#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
170/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
171#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
172
173/* Channel differentiation between external and internal channels */
174#define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000UL /* Marker of internal channel */
175#define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000UL /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
176#define ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT 0x10000000U /* Dummy bit for driver internal usage, not used in ADC channel setting registers CR1 or SQRx */
177#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2 | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
178
179/* Internal register offset for ADC channel sampling time configuration */
180/* (offset placed into a spare area of literal definition) */
181#define ADC_SMPR1_REGOFFSET 0x00000000UL
182#define ADC_SMPR2_REGOFFSET 0x02000000UL
183#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
184
185#define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000UL
186#define ADC_CHANNEL_SMPx_BITOFFSET_POS (20UL) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
187
188/* Definition of channels ID number information to be inserted into */
189/* channels literals definition. */
190#define ADC_CHANNEL_0_NUMBER 0x00000000UL
191#define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
192#define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
193#define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
194#define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
195#define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
196#define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
197#define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
198#define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
199#define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
200#define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
201#define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
202#define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
203#define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
204#define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
205#define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
206#define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
207#define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
208#define ADC_CHANNEL_18_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1 )
209
210/* Definition of channels sampling time information to be inserted into */
211/* channels literals definition. */
212#define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
213#define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
214#define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
215#define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
216#define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
217#define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
218#define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
219#define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
220#define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
221#define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
222#define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
223#define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
224#define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
225#define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
226#define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
227#define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
228#define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
229#define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
230#define ADC_CHANNEL_18_SMP (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP18) */
231
232/* Internal mask for ADC analog watchdog: */
233/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
234/* (concatenation of multiple bits used in different analog watchdogs, */
235/* (feature of several watchdogs not available on all STM32 families)). */
236/* - analog watchdog 1: monitored channel defined by number, */
237/* selection of ADC group (ADC groups regular and-or injected). */
238
239/* Internal register offset for ADC analog watchdog channel configuration */
240#define ADC_AWD_CR1_REGOFFSET 0x00000000UL
241
242#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
243
244#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
245#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
246
247/* Internal register offset for ADC analog watchdog threshold configuration */
248#define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000UL
249#define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001UL
250#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
251
252/* ADC registers bits positions */
253#define ADC_CR1_RES_BITOFFSET_POS (24UL) /* Value equivalent to POSITION_VAL(ADC_CR1_RES) */
254#define ADC_TR_HT_BITOFFSET_POS (16UL) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */
255
256/* ADC internal channels related definitions */
257/* Internal voltage reference VrefInt */
258#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF7A2AU)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
259#define VREFINT_CAL_VREF ( 3300UL) /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */
260/* Temperature sensor */
261#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF7A2CU)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32F4, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
262#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF7A2EU)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32F4, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */
263#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
264#define TEMPSENSOR_CAL2_TEMP (( int32_t) 110) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */
265#define TEMPSENSOR_CAL_VREFANALOG ( 3300UL) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */
266
270
271
272/* Private macros ------------------------------------------------------------*/
276
285#define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
286 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
287
296#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
297 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
298
302
303
304/* Exported types ------------------------------------------------------------*/
305#if defined(USE_FULL_LL_DRIVER)
309
320typedef struct
321{
322 uint32_t CommonClock;
326
327#if defined(ADC_MULTIMODE_SUPPORT)
328 uint32_t Multimode;
332
333 uint32_t MultiDMATransfer;
337
338 uint32_t MultiTwoSamplingDelay;
342#endif /* ADC_MULTIMODE_SUPPORT */
343
344} LL_ADC_CommonInitTypeDef;
345
366typedef struct
367{
368 uint32_t Resolution;
372
373 uint32_t DataAlignment;
377
378 uint32_t SequencersScanMode;
382
383} LL_ADC_InitTypeDef;
384
404typedef struct
405{
406 uint32_t TriggerSource;
412
413 uint32_t SequencerLength;
418
419 uint32_t SequencerDiscont;
425
426 uint32_t ContinuousMode;
431
432 uint32_t DMATransfer;
436
437} LL_ADC_REG_InitTypeDef;
438
458typedef struct
459{
460 uint32_t TriggerSource;
466
467 uint32_t SequencerLength;
472
473 uint32_t SequencerDiscont;
479
480 uint32_t TrigAuto;
485
486} LL_ADC_INJ_InitTypeDef;
487
491#endif /* USE_FULL_LL_DRIVER */
492
493/* Exported constants --------------------------------------------------------*/
497
502#define LL_ADC_FLAG_STRT ADC_SR_STRT
503#define LL_ADC_FLAG_EOCS ADC_SR_EOC
504#define LL_ADC_FLAG_OVR ADC_SR_OVR
505#define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT
506#define LL_ADC_FLAG_JEOS ADC_SR_JEOC
507#define LL_ADC_FLAG_AWD1 ADC_SR_AWD
508#if defined(ADC_MULTIMODE_SUPPORT)
509#define LL_ADC_FLAG_EOCS_MST ADC_CSR_EOC1
510#define LL_ADC_FLAG_EOCS_SLV1 ADC_CSR_EOC2
511#define LL_ADC_FLAG_EOCS_SLV2 ADC_CSR_EOC3
512#define LL_ADC_FLAG_OVR_MST ADC_CSR_OVR1
513#define LL_ADC_FLAG_OVR_SLV1 ADC_CSR_OVR2
514#define LL_ADC_FLAG_OVR_SLV2 ADC_CSR_OVR3
515#define LL_ADC_FLAG_JEOS_MST ADC_CSR_JEOC1
516#define LL_ADC_FLAG_JEOS_SLV1 ADC_CSR_JEOC2
517#define LL_ADC_FLAG_JEOS_SLV2 ADC_CSR_JEOC3
518#define LL_ADC_FLAG_AWD1_MST ADC_CSR_AWD1
519#define LL_ADC_FLAG_AWD1_SLV1 ADC_CSR_AWD2
520#define LL_ADC_FLAG_AWD1_SLV2 ADC_CSR_AWD3
521#endif
525
530#define LL_ADC_IT_EOCS ADC_CR1_EOCIE
531#define LL_ADC_IT_OVR ADC_CR1_OVRIE
532#define LL_ADC_IT_JEOS ADC_CR1_JEOCIE
533#define LL_ADC_IT_AWD1 ADC_CR1_AWDIE
537
541/* List of ADC registers intended to be used (most commonly) with */
542/* DMA transfer. */
543/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
544#define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000UL /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
545#if defined(ADC_MULTIMODE_SUPPORT)
546#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001UL /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
547#endif
551
555#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 0x00000000UL
556#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CCR_ADCPRE_0)
557#define LL_ADC_CLOCK_SYNC_PCLK_DIV6 (ADC_CCR_ADCPRE_1 )
558#define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CCR_ADCPRE_1 | ADC_CCR_ADCPRE_0)
562
566/* Note: Other measurement paths to internal channels may be available */
567/* (connections to other peripherals). */
568/* If they are not listed below, they do not require any specific */
569/* path enable. In this case, Access to measurement path is done */
570/* only by selecting the corresponding ADC internal channel. */
571#define LL_ADC_PATH_INTERNAL_NONE 0x00000000UL
572#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_TSVREFE)
573#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSVREFE)
574#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATE)
578
582#define LL_ADC_RESOLUTION_12B 0x00000000UL
583#define LL_ADC_RESOLUTION_10B ( ADC_CR1_RES_0)
584#define LL_ADC_RESOLUTION_8B (ADC_CR1_RES_1 )
585#define LL_ADC_RESOLUTION_6B (ADC_CR1_RES_1 | ADC_CR1_RES_0)
589
593#define LL_ADC_DATA_ALIGN_RIGHT 0x00000000UL
594#define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN)
598
602#define LL_ADC_SEQ_SCAN_DISABLE 0x00000000UL
603#define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN)
607
611#define LL_ADC_GROUP_REGULAR 0x00000001UL
612#define LL_ADC_GROUP_INJECTED 0x00000002UL
613#define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003UL
617
621#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP)
622#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP)
623#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP)
624#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP)
625#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP)
626#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP)
627#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP)
628#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP)
629#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP)
630#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP)
631#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP)
632#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP)
633#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP)
634#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP)
635#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP)
636#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP)
637#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP)
638#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP)
639#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP)
640#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH)
641#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH)
642#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx)
643#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)
644#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */
645#if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
646#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT)
647#endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
651
655#define LL_ADC_REG_TRIG_SOFTWARE 0x00000000UL
656#define LL_ADC_REG_TRIG_EXT_TIM1_CH1 (ADC_REG_TRIG_EXT_EDGE_DEFAULT)
657#define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
658#define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
659#define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
660#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
661#define LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
662#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
663#define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
664#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
665#define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
666#define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
667#define LL_ADC_REG_TRIG_EXT_TIM5_CH2 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
668#define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
669#define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
670#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
671#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)
675
679#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CR2_EXTEN_0)
680#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CR2_EXTEN_1 )
681#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CR2_EXTEN_1 | ADC_CR2_EXTEN_0)
685
689#define LL_ADC_REG_CONV_SINGLE 0x00000000UL
690#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT)
694
698#define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000UL
699#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CR2_DMA)
700#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DDS | ADC_CR2_DMA)
704
708#define LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV 0x00000000UL
709#define LL_ADC_REG_FLAG_EOC_UNITARY_CONV (ADC_CR2_EOCS)
713
717#define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000UL
718#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0)
719#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 )
720#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0)
721#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 )
722#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0)
723#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 )
724#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
725#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 )
726#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)
727#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 )
728#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
729#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 )
730#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0)
731#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 )
732#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0)
736
740#define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000UL
741#define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN)
742#define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
743#define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)
744#define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
745#define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN)
746#define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
747#define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN)
748#define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN)
752
756#define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)
757#define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)
758#define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)
759#define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)
760#define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)
761#define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)
762#define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)
763#define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)
764#define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)
765#define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS)
766#define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS)
767#define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS)
768#define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS)
769#define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS)
770#define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS)
771#define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS)
775
779#define LL_ADC_INJ_TRIG_SOFTWARE 0x00000000UL
780#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
781#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
782#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
783#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
784#define LL_ADC_INJ_TRIG_EXT_TIM3_CH2 (ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
785#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
786#define LL_ADC_INJ_TRIG_EXT_TIM4_CH1 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
787#define LL_ADC_INJ_TRIG_EXT_TIM4_CH2 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
788#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (ADC_CR2_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
789#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
790#define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
791#define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
792#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
793#define LL_ADC_INJ_TRIG_EXT_TIM8_CH3 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
794#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
795#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)
799
803#define LL_ADC_INJ_TRIG_EXT_RISING ( ADC_CR2_JEXTEN_0)
804#define LL_ADC_INJ_TRIG_EXT_FALLING (ADC_CR2_JEXTEN_1 )
805#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING (ADC_CR2_JEXTEN_1 | ADC_CR2_JEXTEN_0)
809
813#define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000UL
814#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO)
818
819
823#define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000UL
824#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0)
825#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 )
826#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0)
830
834#define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000UL
835#define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN)
839
843#define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001UL)
844#define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002UL)
845#define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003UL)
846#define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004UL)
850
854#define LL_ADC_SAMPLINGTIME_3CYCLES 0x00000000UL
855#define LL_ADC_SAMPLINGTIME_15CYCLES (ADC_SMPR1_SMP10_0)
856#define LL_ADC_SAMPLINGTIME_28CYCLES (ADC_SMPR1_SMP10_1)
857#define LL_ADC_SAMPLINGTIME_56CYCLES (ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0)
858#define LL_ADC_SAMPLINGTIME_84CYCLES (ADC_SMPR1_SMP10_2)
859#define LL_ADC_SAMPLINGTIME_112CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0)
860#define LL_ADC_SAMPLINGTIME_144CYCLES (ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1)
861#define LL_ADC_SAMPLINGTIME_480CYCLES (ADC_SMPR1_SMP10)
865
869#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET)
873
877#define LL_ADC_AWD_DISABLE 0x00000000UL
878#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN )
879#define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN )
880#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN )
881#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
882#define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
883#define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
884#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
885#define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
886#define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
887#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
888#define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
889#define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
890#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
891#define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
892#define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
893#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
894#define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
895#define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
896#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
897#define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
898#define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
899#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
900#define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
901#define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
902#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
903#define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
904#define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
905#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
906#define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
907#define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
908#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
909#define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
910#define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
911#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
912#define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
913#define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
914#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
915#define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
916#define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
917#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
918#define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
919#define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
920#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
921#define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
922#define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
923#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
924#define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
925#define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
926#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
927#define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
928#define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
929#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
930#define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
931#define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
932#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
933#define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
934#define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
935#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
936#define LL_ADC_AWD_CHANNEL_18_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
937#define LL_ADC_AWD_CHANNEL_18_REG_INJ ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
938#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
939#define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
940#define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
941#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
942#define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
943#define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
944#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx)
945#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
946#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
947#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
948#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */
949#if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
950#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
951#define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL)
952#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
953#endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
957
961#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET)
962#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET)
966
967#if defined(ADC_MULTIMODE_SUPPORT)
971#define LL_ADC_MULTI_INDEPENDENT 0x00000000UL
972#define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 )
973#define LL_ADC_MULTI_DUAL_REG_INTERL ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)
974#define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)
975#define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0)
976#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CCR_MULTI_0)
977#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CCR_MULTI_1 )
978#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM ( ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)
979#if defined(ADC3)
980#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0)
981#define LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1 )
982#define LL_ADC_MULTI_TRIPLE_INJ_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0)
983#define LL_ADC_MULTI_TRIPLE_REG_SIMULT (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 )
984#define LL_ADC_MULTI_TRIPLE_REG_INTERL (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0)
985#define LL_ADC_MULTI_TRIPLE_INJ_ALTERN (ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0)
986#endif
990
994#define LL_ADC_MULTI_REG_DMA_EACH_ADC 0x00000000UL
995#define LL_ADC_MULTI_REG_DMA_LIMIT_1 ( ADC_CCR_DMA_0)
996#define LL_ADC_MULTI_REG_DMA_LIMIT_2 ( ADC_CCR_DMA_1 )
997#define LL_ADC_MULTI_REG_DMA_LIMIT_3 ( ADC_CCR_DMA_1 | ADC_CCR_DMA_0)
998#define LL_ADC_MULTI_REG_DMA_UNLMT_1 (ADC_CCR_DDS | ADC_CCR_DMA_0)
999#define LL_ADC_MULTI_REG_DMA_UNLMT_2 (ADC_CCR_DDS | ADC_CCR_DMA_1 )
1000#define LL_ADC_MULTI_REG_DMA_UNLMT_3 (ADC_CCR_DDS | ADC_CCR_DMA_1 | ADC_CCR_DMA_0)
1004
1008#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES 0x00000000UL
1009#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES ( ADC_CCR_DELAY_0)
1010#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES ( ADC_CCR_DELAY_1 )
1011#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES ( ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1012#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES ( ADC_CCR_DELAY_2 )
1013#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)
1014#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 )
1015#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES ( ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1016#define LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES (ADC_CCR_DELAY_3 )
1017#define LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)
1018#define LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 )
1019#define LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1020#define LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 )
1021#define LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)
1022#define LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 )
1023#define LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)
1027
1031#define LL_ADC_MULTI_MASTER ( ADC_CDR_RDATA_MST)
1032#define LL_ADC_MULTI_SLAVE (ADC_CDR_RDATA_SLV )
1033#define LL_ADC_MULTI_MASTER_SLAVE (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST)
1037
1038#endif /* ADC_MULTIMODE_SUPPORT */
1039
1040
1048
1049/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
1050/* not timeout values. */
1051/* Timeout values for ADC operations are dependent to device clock */
1052/* configuration (system clock versus ADC clock), */
1053/* and therefore must be defined in user application. */
1054/* Indications for estimation of ADC timeout delays, for this */
1055/* STM32 series: */
1056/* - ADC enable time: maximum delay is 2us */
1057/* (refer to device datasheet, parameter "tSTAB") */
1058/* - ADC conversion time: duration depending on ADC clock and ADC */
1059/* configuration. */
1060/* (refer to device reference manual, section "Timing") */
1061
1062/* Delay for internal voltage reference stabilization time. */
1063/* Delay set to maximum value (refer to device datasheet, */
1064/* parameter "tSTART"). */
1065/* Unit: us */
1066#define LL_ADC_DELAY_VREFINT_STAB_US ( 10UL)
1067
1068/* Delay for temperature sensor stabilization time. */
1069/* Literal set to maximum value (refer to device datasheet, */
1070/* parameter "tSTART"). */
1071/* Unit: us */
1072#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10UL)
1073
1077
1081
1082
1083/* Exported macro ------------------------------------------------------------*/
1087
1091
1099#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1100
1107#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1111
1115
1153#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1154 (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
1155
1193#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1194 (((__DECIMAL_NB__) <= 9UL) \
1195 ? ( \
1196 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1197 (ADC_SMPR2_REGOFFSET | (((uint32_t) (3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1198 ) \
1199 : \
1200 ( \
1201 ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1202 (ADC_SMPR1_REGOFFSET | (((uint32_t) (3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1203 ) \
1204 )
1205
1252#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1253 (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
1254
1315#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1316 ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1317
1342#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1343 ( \
1344 ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1345 ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \
1346 ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT) \
1347 )
1465#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1466 (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1467 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1468 : \
1469 ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1470 ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
1471 : \
1472 (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1473 )
1474
1494#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1495 ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL )))
1496
1516#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1517 ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL )))
1518
1519#if defined(ADC_MULTIMODE_SUPPORT)
1533#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
1534 (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
1535#endif
1536
1547#if defined(ADC1) && defined(ADC2) && defined(ADC3)
1548#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1549 (ADC123_COMMON)
1550#elif defined(ADC1) && defined(ADC2)
1551#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1552 (ADC12_COMMON)
1553#else
1554#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1555 (ADC1_COMMON)
1556#endif
1557
1575#if defined(ADC1) && defined(ADC2) && defined(ADC3)
1576#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1577 (LL_ADC_IsEnabled(ADC1) | \
1578 LL_ADC_IsEnabled(ADC2) | \
1579 LL_ADC_IsEnabled(ADC3) )
1580#elif defined(ADC1) && defined(ADC2)
1581#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1582 (LL_ADC_IsEnabled(ADC1) | \
1583 LL_ADC_IsEnabled(ADC2) )
1584#else
1585#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1586 (LL_ADC_IsEnabled(ADC1))
1587#endif
1588
1602#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1603 (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)))
1604
1623#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \
1624 (((__DATA__) \
1625 << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL))) \
1626 >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CR1_RES_BITOFFSET_POS - 1UL)) \
1627 )
1628
1645#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1646 __ADC_DATA__,\
1647 __ADC_RESOLUTION__) \
1648 ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1649 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1650 )
1651
1677#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
1678 __ADC_RESOLUTION__) \
1679 (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \
1680 / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \
1681 (__ADC_RESOLUTION__), \
1682 LL_ADC_RESOLUTION_12B))
1683
1684/* Note: On device STM32F4x9, calibration parameter TS_CAL2 is not available. */
1685/* Therefore, helper macro __LL_ADC_CALC_TEMPERATURE() is not available.*/
1686/* Use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). */
1687#if !defined(STM32F469) && !defined(STM32F479xx) && !defined(STM32F429xx) && !defined(STM32F439xx)
1733#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
1734 __TEMPSENSOR_ADC_DATA__,\
1735 __ADC_RESOLUTION__) \
1736 (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \
1737 (__ADC_RESOLUTION__), \
1738 LL_ADC_RESOLUTION_12B) \
1739 * (__VREFANALOG_VOLTAGE__)) \
1740 / TEMPSENSOR_CAL_VREFANALOG) \
1741 - (int32_t) *TEMPSENSOR_CAL1_ADDR) \
1742 ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \
1743 ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
1744 ) + TEMPSENSOR_CAL1_TEMP \
1745 )
1746#endif
1747
1792#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1793 __TEMPSENSOR_TYP_CALX_V__,\
1794 __TEMPSENSOR_CALX_TEMP__,\
1795 __VREFANALOG_VOLTAGE__,\
1796 __TEMPSENSOR_ADC_DATA__,\
1797 __ADC_RESOLUTION__) \
1798 ((( ( \
1799 (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1800 * 1000) \
1801 - \
1802 (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1803 / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1804 * 1000) \
1805 ) \
1806 ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
1807 ) + (__TEMPSENSOR_CALX_TEMP__) \
1808 )
1809
1813
1817
1818
1819/* Exported functions --------------------------------------------------------*/
1823
1827/* Note: LL ADC functions to set DMA transfer are located into sections of */
1828/* configuration of ADC instance, groups and multimode (if available): */
1829/* @ref LL_ADC_REG_SetDMATransfer(), ... */
1830
1861#if defined(ADC_MULTIMODE_SUPPORT)
1862__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
1863{
1864 uint32_t data_reg_addr = 0UL;
1865
1866 if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
1867 {
1868 /* Retrieve address of register DR */
1869 data_reg_addr = (uint32_t) & (ADCx->DR);
1870 }
1871 else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
1872 {
1873 /* Retrieve address of register CDR */
1874 data_reg_addr = (uint32_t) & ((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
1875 }
1876
1877 return data_reg_addr;
1878}
1879#else
1880__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1881{
1882 /* Prevent unused argument compilation warning */
1883 (void)Register;
1884
1885 /* Retrieve address of register DR */
1886 return (uint32_t) & (ADCx->DR);
1887}
1888#endif
1889
1893
1897
1910__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
1911{
1912 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE, CommonClock);
1913}
1914
1926__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
1927{
1928 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_ADCPRE));
1929}
1930
1959__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1960{
1961 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE, PathInternal);
1962}
1963
1980__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
1981{
1982 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_TSVREFE | ADC_CCR_VBATE));
1983}
1984
1988
1992
2006__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
2007{
2008 MODIFY_REG(ADCx->CR1, ADC_CR1_RES, Resolution);
2009}
2010
2023__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
2024{
2025 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_RES));
2026}
2027
2039__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
2040{
2041 MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
2042}
2043
2054__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
2055{
2056 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
2057}
2058
2080__STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
2081{
2082 MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
2083}
2084
2105__STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(const ADC_TypeDef *ADCx)
2106{
2107 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
2108}
2109
2113
2117
2149__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2150{
2151 /* Note: On this STM32 series, ADC group regular external trigger edge */
2152 /* is used to perform a ADC conversion start. */
2153 /* This function does not set external trigger edge. */
2154 /* This feature is set using function */
2155 /* @ref LL_ADC_REG_StartConversionExtTrig(). */
2156 MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
2157}
2158
2193__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
2194{
2195 uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL | ADC_CR2_EXTEN);
2196
2197 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2198 /* corresponding to ADC_CR2_EXTEN {0; 1; 2; 3}. */
2199 uint32_t ShiftExten = ((TriggerSource & ADC_CR2_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
2200
2201 /* Set bitfield corresponding to ADC_CR2_EXTEN and ADC_CR2_EXTSEL */
2202 /* to match with triggers literals definition. */
2203 return ((TriggerSource
2204 & (ADC_REG_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_EXTSEL)
2205 | ((ADC_REG_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_EXTEN)
2206 );
2207}
2208
2220__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
2221{
2222 return (READ_BIT(ADCx->CR2, ADC_CR2_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CR2_EXTEN));
2223}
2224
2237__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
2238{
2239 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTEN));
2240}
2241
2242
2299__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2300{
2301 MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
2302}
2303
2359__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
2360{
2361 return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
2362}
2363
2387__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2388{
2389 MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
2390}
2391
2410__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
2411{
2412 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
2413}
2414
2493__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2494{
2495 /* Set bits with content of parameter "Channel" with bits position */
2496 /* in register and register position depending on parameter "Rank". */
2497 /* Parameters "Rank" and "Channel" are used with masks because containing */
2498 /* other bits reserved for other purpose. */
2499 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2500
2501 MODIFY_REG(*preg,
2502 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
2503 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
2504}
2505
2590__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
2591{
2592 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2593
2594 return (uint32_t)(READ_BIT(*preg,
2595 ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
2596 >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
2597 );
2598}
2599
2615__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
2616{
2617 MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
2618}
2619
2632__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
2633{
2634 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
2635}
2636
2668__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
2669{
2670 MODIFY_REG(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS, DMATransfer);
2671}
2672
2703__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
2704{
2705 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA | ADC_CR2_DDS));
2706}
2707
2725__STATIC_INLINE void LL_ADC_REG_SetFlagEndOfConversion(ADC_TypeDef *ADCx, uint32_t EocSelection)
2726{
2727 MODIFY_REG(ADCx->CR2, ADC_CR2_EOCS, EocSelection);
2728}
2729
2740__STATIC_INLINE uint32_t LL_ADC_REG_GetFlagEndOfConversion(const ADC_TypeDef *ADCx)
2741{
2742 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EOCS));
2743}
2744
2748
2752
2784__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2785{
2786 /* Note: On this STM32 series, ADC group injected external trigger edge */
2787 /* is used to perform a ADC conversion start. */
2788 /* This function does not set external trigger edge. */
2789 /* This feature is set using function */
2790 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */
2791 MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
2792}
2793
2828__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx)
2829{
2830 uint32_t TriggerSource = READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL | ADC_CR2_JEXTEN);
2831
2832 /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */
2833 /* corresponding to ADC_CR2_JEXTEN {0; 1; 2; 3}. */
2834 uint32_t ShiftExten = ((TriggerSource & ADC_CR2_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
2835
2836 /* Set bitfield corresponding to ADC_CR2_JEXTEN and ADC_CR2_JEXTSEL */
2837 /* to match with triggers literals definition. */
2838 return ((TriggerSource
2839 & (ADC_INJ_TRIG_SOURCE_MASK << ShiftExten) & ADC_CR2_JEXTSEL)
2840 | ((ADC_INJ_TRIG_EDGE_MASK << ShiftExten) & ADC_CR2_JEXTEN)
2841 );
2842}
2843
2855__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
2856{
2857 return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_CR2_JEXTEN));
2858}
2859
2870__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx)
2871{
2872 return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTEN));
2873}
2874
2898__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2899{
2900 MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
2901}
2902
2925__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx)
2926{
2927 return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
2928}
2929
2943__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2944{
2945 MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
2946}
2947
2958__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx)
2959{
2960 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
2961}
2962
3010__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
3011{
3012 /* Set bits with content of parameter "Channel" with bits position */
3013 /* in register depending on parameter "Rank". */
3014 /* Parameters "Rank" and "Channel" are used with masks because containing */
3015 /* other bits reserved for other purpose. */
3016 uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL;
3017
3018 MODIFY_REG(ADCx->JSQR,
3019 ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))),
3020 (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))));
3021}
3022
3079__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
3080{
3081 uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1UL;
3082
3083 return (uint32_t)(READ_BIT(ADCx->JSQR,
3084 ADC_CHANNEL_ID_NUMBER_MASK << (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1))))
3085 >> (5UL * (uint8_t)(((Rank) + 3UL) - (tmpreg1)))
3086 );
3087}
3088
3115__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
3116{
3117 MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
3118}
3119
3129__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx)
3130{
3131 return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
3132}
3133
3159__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
3160{
3161 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3162
3163 MODIFY_REG(*preg,
3164 ADC_JOFR1_JOFFSET1,
3165 OffsetLevel);
3166}
3167
3186__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(const ADC_TypeDef *ADCx, uint32_t Rank)
3187{
3188 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
3189
3190 return (uint32_t)(READ_BIT(*preg,
3191 ADC_JOFR1_JOFFSET1)
3192 );
3193}
3194
3198
3202
3279__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
3280{
3281 /* Set bits with content of parameter "SamplingTime" with bits position */
3282 /* in register and register position depending on parameter "Channel". */
3283 /* Parameter "Channel" is used with masks because containing */
3284 /* other bits reserved for other purpose. */
3285 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3286
3287 MODIFY_REG(*preg,
3288 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
3289 SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
3290}
3291
3356__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
3357{
3358 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
3359
3360 return (uint32_t)(READ_BIT(*preg,
3361 ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
3362 >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
3363 );
3364}
3365
3369
3373
3470__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
3471{
3472 MODIFY_REG(ADCx->CR1,
3473 (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
3474 AWDChannelGroup);
3475}
3476
3566__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx)
3567{
3568 return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
3569}
3570
3593__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
3594{
3595 __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3596
3597 MODIFY_REG(*preg,
3598 ADC_HTR_HT,
3599 AWDThresholdValue);
3600}
3601
3616__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
3617{
3618 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3619
3620 return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
3621}
3622
3626
3630
3631#if defined(ADC_MULTIMODE_SUPPORT)
3658__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
3659{
3660 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MULTI, Multimode);
3661}
3662
3688__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
3689{
3690 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MULTI));
3691}
3692
3737__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
3738{
3739 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS, MultiDMATransfer);
3740}
3741
3785__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
3786{
3787 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DMA | ADC_CCR_DDS));
3788}
3789
3819__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
3820{
3821 MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
3822}
3823
3847__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON)
3848{
3849 return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
3850}
3851#endif /* ADC_MULTIMODE_SUPPORT */
3852
3859
3870__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
3871{
3872 SET_BIT(ADCx->CR2, ADC_CR2_ADON);
3873}
3874
3881__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
3882{
3883 CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
3884}
3885
3892__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
3893{
3894 return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
3895}
3896
3900
3904
3921__STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
3922{
3923 SET_BIT(ADCx->CR2, ADC_CR2_SWSTART);
3924}
3925
3942__STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3943{
3944 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
3945}
3946
3960__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
3961{
3962 CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTEN);
3963}
3964
3974__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
3975{
3976 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3977}
3978
3989__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
3990{
3991 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3992}
3993
4004__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
4005{
4006 return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4007}
4008
4019__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
4020{
4021 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4022}
4023
4034__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
4035{
4036 return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
4037}
4038
4039#if defined(ADC_MULTIMODE_SUPPORT)
4061__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)
4062{
4063 return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
4064 ADC_DR_ADC2DATA)
4065 >> POSITION_VAL(ConversionData)
4066 );
4067}
4068#endif /* ADC_MULTIMODE_SUPPORT */
4069
4073
4077
4094__STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
4095{
4096 SET_BIT(ADCx->CR2, ADC_CR2_JSWSTART);
4097}
4098
4115__STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
4116{
4117 SET_BIT(ADCx->CR2, ExternalTriggerEdge);
4118}
4119
4133__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
4134{
4135 CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTEN);
4136}
4137
4155__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
4156{
4157 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4158
4159 return (uint32_t)(READ_BIT(*preg,
4160 ADC_JDR1_JDATA)
4161 );
4162}
4163
4182__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
4183{
4184 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4185
4186 return (uint16_t)(READ_BIT(*preg,
4187 ADC_JDR1_JDATA)
4188 );
4189}
4190
4209__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
4210{
4211 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4212
4213 return (uint16_t)(READ_BIT(*preg,
4214 ADC_JDR1_JDATA)
4215 );
4216}
4217
4236__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
4237{
4238 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4239
4240 return (uint8_t)(READ_BIT(*preg,
4241 ADC_JDR1_JDATA)
4242 );
4243}
4244
4263__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx, uint32_t Rank)
4264{
4265 __IO uint32_t const *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
4266
4267 return (uint8_t)(READ_BIT(*preg,
4268 ADC_JDR1_JDATA)
4269 );
4270}
4271
4275
4279
4290__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCS(const ADC_TypeDef *ADCx)
4291{
4292 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOCS) == (LL_ADC_FLAG_EOCS));
4293}
4294
4301__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
4302{
4303 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR));
4304}
4305
4306
4313__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
4314{
4315 /* Note: on this STM32 series, there is no flag ADC group injected */
4316 /* end of unitary conversion. */
4317 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4318 /* in other STM32 families). */
4319 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
4320}
4321
4328__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
4329{
4330 return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
4331}
4332
4343__STATIC_INLINE void LL_ADC_ClearFlag_EOCS(ADC_TypeDef *ADCx)
4344{
4345 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOCS);
4346}
4347
4354__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
4355{
4356 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_OVR);
4357}
4358
4359
4366__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
4367{
4368 /* Note: on this STM32 series, there is no flag ADC group injected */
4369 /* end of unitary conversion. */
4370 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4371 /* in other STM32 families). */
4372 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
4373}
4374
4381__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
4382{
4383 WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
4384}
4385
4386#if defined(ADC_MULTIMODE_SUPPORT)
4398__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOCS(const ADC_Common_TypeDef *ADCxy_COMMON)
4399{
4400 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_MST) == (LL_ADC_FLAG_EOCS_MST));
4401}
4402
4414__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_EOCS(const ADC_Common_TypeDef *ADCxy_COMMON)
4415{
4416 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV1) == (LL_ADC_FLAG_EOCS_SLV1));
4417}
4418
4430__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_EOCS(const ADC_Common_TypeDef *ADCxy_COMMON)
4431{
4432 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOCS_SLV2) == (LL_ADC_FLAG_EOCS_SLV2));
4433}
4441__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
4442{
4443 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST));
4444}
4445
4453__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
4454{
4455 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV1) == (LL_ADC_FLAG_OVR_SLV1));
4456}
4457
4465__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
4466{
4467 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV2) == (LL_ADC_FLAG_OVR_SLV2));
4468}
4469
4470
4478__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
4479{
4480 /* Note: on this STM32 series, there is no flag ADC group injected */
4481 /* end of unitary conversion. */
4482 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4483 /* in other STM32 families). */
4484 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC1) == (ADC_CSR_JEOC1));
4485}
4486
4494__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
4495{
4496 /* Note: on this STM32 series, there is no flag ADC group injected */
4497 /* end of unitary conversion. */
4498 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4499 /* in other STM32 families). */
4500 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC2) == (ADC_CSR_JEOC2));
4501}
4502
4510__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
4511{
4512 /* Note: on this STM32 series, there is no flag ADC group injected */
4513 /* end of unitary conversion. */
4514 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4515 /* in other STM32 families). */
4516 return (READ_BIT(ADCxy_COMMON->CSR, ADC_CSR_JEOC3) == (ADC_CSR_JEOC3));
4517}
4518
4526__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
4527{
4528 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST));
4529}
4530
4538__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV1_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
4539{
4540 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV1) == (LL_ADC_FLAG_AWD1_SLV1));
4541}
4542
4550__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV2_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
4551{
4552 return (READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV2) == (LL_ADC_FLAG_AWD1_SLV2));
4553}
4554
4555#endif /* ADC_MULTIMODE_SUPPORT */
4556
4560
4564
4575__STATIC_INLINE void LL_ADC_EnableIT_EOCS(ADC_TypeDef *ADCx)
4576{
4577 SET_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4578}
4579
4586__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
4587{
4588 SET_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4589}
4590
4591
4598__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
4599{
4600 /* Note: on this STM32 series, there is no flag ADC group injected */
4601 /* end of unitary conversion. */
4602 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4603 /* in other STM32 families). */
4604 SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4605}
4606
4613__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
4614{
4615 SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4616}
4617
4628__STATIC_INLINE void LL_ADC_DisableIT_EOCS(ADC_TypeDef *ADCx)
4629{
4630 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_EOCS);
4631}
4632
4639__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
4640{
4641 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_OVR);
4642}
4643
4644
4651__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
4652{
4653 /* Note: on this STM32 series, there is no flag ADC group injected */
4654 /* end of unitary conversion. */
4655 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4656 /* in other STM32 families). */
4657 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
4658}
4659
4666__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
4667{
4668 CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
4669}
4670
4682__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCS(const ADC_TypeDef *ADCx)
4683{
4684 return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOCS) == (LL_ADC_IT_EOCS));
4685}
4686
4694__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
4695{
4696 return (READ_BIT(ADCx->CR1, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR));
4697}
4698
4699
4707__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
4708{
4709 /* Note: on this STM32 series, there is no flag ADC group injected */
4710 /* end of unitary conversion. */
4711 /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
4712 /* in other STM32 families). */
4713 return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
4714}
4715
4723__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
4724{
4725 return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
4726}
4727
4731
4732#if defined(USE_FULL_LL_DRIVER)
4736
4737/* Initialization of some features of ADC common parameters and multimode */
4738ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
4739ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4740void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
4741
4742/* De-initialization of ADC instance, ADC group regular and ADC group injected */
4743/* (availability of ADC group injected depends on STM32 families) */
4744ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
4745
4746/* Initialization of some features of ADC instance */
4747ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
4748void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
4749
4750/* Initialization of some features of ADC instance and ADC group regular */
4751ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4752void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
4753
4754/* Initialization of some features of ADC instance and ADC group injected */
4755ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4756void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
4757
4761#endif /* USE_FULL_LL_DRIVER */
4762
4766
4770
4771#endif /* ADC1 || ADC2 || ADC3 */
4772
4776
4777#ifdef __cplusplus
4778}
4779#endif
4780
4781#endif /* __STM32F4xx_LL_ADC_H */
4782