20#ifndef STM32F4xx_HAL_SPI_H
21#define STM32F4xx_HAL_SPI_H
136#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
151#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
157 HAL_SPI_TX_COMPLETE_CB_ID = 0x00U,
158 HAL_SPI_RX_COMPLETE_CB_ID = 0x01U,
159 HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U,
160 HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U,
161 HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U,
162 HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U,
163 HAL_SPI_ERROR_CB_ID = 0x06U,
164 HAL_SPI_ABORT_CB_ID = 0x07U,
165 HAL_SPI_MSPINIT_CB_ID = 0x08U,
166 HAL_SPI_MSPDEINIT_CB_ID = 0x09U
168} HAL_SPI_CallbackIDTypeDef;
188#define HAL_SPI_ERROR_NONE (0x00000000U)
189#define HAL_SPI_ERROR_MODF (0x00000001U)
190#define HAL_SPI_ERROR_CRC (0x00000002U)
191#define HAL_SPI_ERROR_OVR (0x00000004U)
192#define HAL_SPI_ERROR_FRE (0x00000008U)
193#define HAL_SPI_ERROR_DMA (0x00000010U)
194#define HAL_SPI_ERROR_FLAG (0x00000020U)
195#define HAL_SPI_ERROR_ABORT (0x00000040U)
196#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
197#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U)
206#define SPI_MODE_SLAVE (0x00000000U)
207#define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
215#define SPI_DIRECTION_2LINES (0x00000000U)
216#define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
217#define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
225#define SPI_DATASIZE_8BIT (0x00000000U)
226#define SPI_DATASIZE_16BIT SPI_CR1_DFF
234#define SPI_POLARITY_LOW (0x00000000U)
235#define SPI_POLARITY_HIGH SPI_CR1_CPOL
243#define SPI_PHASE_1EDGE (0x00000000U)
244#define SPI_PHASE_2EDGE SPI_CR1_CPHA
252#define SPI_NSS_SOFT SPI_CR1_SSM
253#define SPI_NSS_HARD_INPUT (0x00000000U)
254#define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U)
262#define SPI_BAUDRATEPRESCALER_2 (0x00000000U)
263#define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0)
264#define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1)
265#define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0)
266#define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2)
267#define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0)
268#define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1)
269#define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
277#define SPI_FIRSTBIT_MSB (0x00000000U)
278#define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
286#define SPI_TIMODE_DISABLE (0x00000000U)
287#define SPI_TIMODE_ENABLE SPI_CR2_FRF
295#define SPI_CRCCALCULATION_DISABLE (0x00000000U)
296#define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN
304#define SPI_IT_TXE SPI_CR2_TXEIE
305#define SPI_IT_RXNE SPI_CR2_RXNEIE
306#define SPI_IT_ERR SPI_CR2_ERRIE
314#define SPI_FLAG_RXNE SPI_SR_RXNE
315#define SPI_FLAG_TXE SPI_SR_TXE
316#define SPI_FLAG_BSY SPI_SR_BSY
317#define SPI_FLAG_CRCERR SPI_SR_CRCERR
318#define SPI_FLAG_MODF SPI_SR_MODF
319#define SPI_FLAG_OVR SPI_SR_OVR
320#define SPI_FLAG_FRE SPI_SR_FRE
321#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
322 | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE)
341#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
342#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \
344 (__HANDLE__)->State = HAL_SPI_STATE_RESET; \
345 (__HANDLE__)->MspInitCallback = NULL; \
346 (__HANDLE__)->MspDeInitCallback = NULL; \
349#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
362#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
374#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
386#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
387 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
403#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
410#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
417#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \
419 __IO uint32_t tmpreg_modf = 0x00U; \
420 tmpreg_modf = (__HANDLE__)->Instance->SR; \
421 CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \
422 UNUSED(tmpreg_modf); \
430#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \
432 __IO uint32_t tmpreg_ovr = 0x00U; \
433 tmpreg_ovr = (__HANDLE__)->Instance->DR; \
434 tmpreg_ovr = (__HANDLE__)->Instance->SR; \
435 UNUSED(tmpreg_ovr); \
443#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
445 __IO uint32_t tmpreg_fre = 0x00U; \
446 tmpreg_fre = (__HANDLE__)->Instance->SR; \
447 UNUSED(tmpreg_fre); \
455#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
462#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
478#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
485#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
492#define SPI_RESET_CRC(__HANDLE__) \
494 CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
495 SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \
511#define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \
512 ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET)
523#define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \
524 (__INTERRUPT__)) ? SET : RESET)
531#define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \
532 ((__MODE__) == SPI_MODE_MASTER))
539#define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
540 ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \
541 ((__MODE__) == SPI_DIRECTION_1LINE))
547#define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES)
553#define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \
554 ((__MODE__) == SPI_DIRECTION_1LINE))
561#define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \
562 ((__DATASIZE__) == SPI_DATASIZE_8BIT))
569#define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \
570 ((__CPOL__) == SPI_POLARITY_HIGH))
577#define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \
578 ((__CPHA__) == SPI_PHASE_2EDGE))
585#define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \
586 ((__NSS__) == SPI_NSS_HARD_INPUT) || \
587 ((__NSS__) == SPI_NSS_HARD_OUTPUT))
594#define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \
595 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \
596 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \
597 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \
598 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \
599 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \
600 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \
601 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256))
608#define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \
609 ((__BIT__) == SPI_FIRSTBIT_LSB))
616#define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \
617 ((__MODE__) == SPI_TIMODE_ENABLE))
624#define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \
625 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE))
632#define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \
633 ((__POLYNOMIAL__) <= 0xFFFFU) && \
634 (((__POLYNOMIAL__)&0x1U) != 0U))
640#define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL)
661#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
663 pSPI_CallbackTypeDef pCallback);
677 uint16_t Size, uint32_t Timeout);
struct __DMA_HandleTypeDef DMA_HandleTypeDef
DMA handle Structure definition.
void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size)
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi)
uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi)
HAL_SPI_StateTypeDef
HAL SPI State structure definition.
struct __SPI_HandleTypeDef SPI_HandleTypeDef
SPI handle Structure definition.
@ HAL_SPI_STATE_BUSY_TX_RX
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL Status structures definition.
HAL_LockTypeDef
HAL Lock structures definition.
SPI Configuration Structure definition.
uint32_t BaudRatePrescaler
SPI handle Structure definition.
DMA_HandleTypeDef * hdmarx
volatile HAL_SPI_StateTypeDef State
volatile uint32_t ErrorCode
void(* TxISR)(struct __SPI_HandleTypeDef *hspi)
volatile uint16_t TxXferCount
void(* RxISR)(struct __SPI_HandleTypeDef *hspi)
volatile uint16_t RxXferCount
DMA_HandleTypeDef * hdmatx
const uint8_t * pTxBuffPtr