STM32F4xx HAL Driver master
STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_hal_dma2d.h
Go to the documentation of this file.
1
18
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32F4xx_HAL_DMA2D_H
21#define STM32F4xx_HAL_DMA2D_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32f4xx_hal_def.h"
29
33
34#if defined (DMA2D)
35
40
41/* Exported types ------------------------------------------------------------*/
45#define MAX_DMA2D_LAYER 2U
46
50typedef struct
51{
52 uint32_t *pCLUT;
53
54 uint32_t CLUTColorMode;
56
57 uint32_t Size;
59} DMA2D_CLUTCfgTypeDef;
60
64typedef struct
65{
66 uint32_t Mode;
68
69 uint32_t ColorMode;
71
72 uint32_t OutputOffset;
75
76
77
78
79} DMA2D_InitTypeDef;
80
81
85typedef struct
86{
87 uint32_t InputOffset;
90
91 uint32_t InputColorMode;
93
94 uint32_t AlphaMode;
96
97 uint32_t InputAlpha;
108
109
110} DMA2D_LayerCfgTypeDef;
111
115typedef enum
116{
117 HAL_DMA2D_STATE_RESET = 0x00U,
118 HAL_DMA2D_STATE_READY = 0x01U,
119 HAL_DMA2D_STATE_BUSY = 0x02U,
120 HAL_DMA2D_STATE_TIMEOUT = 0x03U,
121 HAL_DMA2D_STATE_ERROR = 0x04U,
122 HAL_DMA2D_STATE_SUSPEND = 0x05U
123} HAL_DMA2D_StateTypeDef;
124
128typedef struct __DMA2D_HandleTypeDef
129{
130 DMA2D_TypeDef *Instance;
131
132 DMA2D_InitTypeDef Init;
133
134 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
135
136 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
137
138#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
139 void (* LineEventCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
140
141 void (* CLUTLoadingCpltCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
142
143 void (* MspInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
144
145 void (* MspDeInitCallback)(struct __DMA2D_HandleTypeDef *hdma2d);
146
147#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
148
149 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER];
150
151 HAL_LockTypeDef Lock;
152
153 __IO HAL_DMA2D_StateTypeDef State;
154
155 __IO uint32_t ErrorCode;
156} DMA2D_HandleTypeDef;
157
158#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
162typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef *hdma2d);
163#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
167
168/* Exported constants --------------------------------------------------------*/
172
176#define HAL_DMA2D_ERROR_NONE 0x00000000U
177#define HAL_DMA2D_ERROR_TE 0x00000001U
178#define HAL_DMA2D_ERROR_CE 0x00000002U
179#define HAL_DMA2D_ERROR_CAE 0x00000004U
180#define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U
181#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
182#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U
183#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
184
188
192#define DMA2D_M2M 0x00000000U
193#define DMA2D_M2M_PFC DMA2D_CR_MODE_0
194#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1
195#define DMA2D_R2M DMA2D_CR_MODE
199
203#define DMA2D_OUTPUT_ARGB8888 0x00000000U
204#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0
205#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1
206#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1)
207#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2
211
215#define DMA2D_INPUT_ARGB8888 0x00000000U
216#define DMA2D_INPUT_RGB888 0x00000001U
217#define DMA2D_INPUT_RGB565 0x00000002U
218#define DMA2D_INPUT_ARGB1555 0x00000003U
219#define DMA2D_INPUT_ARGB4444 0x00000004U
220#define DMA2D_INPUT_L8 0x00000005U
221#define DMA2D_INPUT_AL44 0x00000006U
222#define DMA2D_INPUT_AL88 0x00000007U
223#define DMA2D_INPUT_L4 0x00000008U
224#define DMA2D_INPUT_A8 0x00000009U
225#define DMA2D_INPUT_A4 0x0000000AU
229
233#define DMA2D_NO_MODIF_ALPHA 0x00000000U
234#define DMA2D_REPLACE_ALPHA 0x00000001U
235#define DMA2D_COMBINE_ALPHA 0x00000002U
240
241
242
243
244
245
249#define DMA2D_CCM_ARGB8888 0x00000000U
250#define DMA2D_CCM_RGB888 0x00000001U
254
258#define DMA2D_IT_CE DMA2D_CR_CEIE
259#define DMA2D_IT_CTC DMA2D_CR_CTCIE
260#define DMA2D_IT_CAE DMA2D_CR_CAEIE
261#define DMA2D_IT_TW DMA2D_CR_TWIE
262#define DMA2D_IT_TC DMA2D_CR_TCIE
263#define DMA2D_IT_TE DMA2D_CR_TEIE
267
271#define DMA2D_FLAG_CE DMA2D_ISR_CEIF
272#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF
273#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF
274#define DMA2D_FLAG_TW DMA2D_ISR_TWIF
275#define DMA2D_FLAG_TC DMA2D_ISR_TCIF
276#define DMA2D_FLAG_TE DMA2D_ISR_TEIF
280
281#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
285typedef enum
286{
287 HAL_DMA2D_MSPINIT_CB_ID = 0x00U,
288 HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U,
289 HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U,
290 HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U,
291 HAL_DMA2D_LINEEVENT_CB_ID = 0x04U,
292 HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U,
293} HAL_DMA2D_CallbackIDTypeDef;
294#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
295
296
300/* Exported macros ------------------------------------------------------------*/
304
309#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
310#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \
311 (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\
312 (__HANDLE__)->MspInitCallback = NULL; \
313 (__HANDLE__)->MspDeInitCallback = NULL; \
314 }while(0)
315#else
316#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
317#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
318
319
325#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
326
327
328/* Interrupt & Flag management */
342#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
343
357#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
358
372#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
373
387#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
388
402#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
403
407
408/* Exported functions --------------------------------------------------------*/
412
416
417/* Initialization and de-initialization functions *******************************/
418HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
419HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d);
420void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d);
421void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d);
422/* Callbacks Register/UnRegister functions ***********************************/
423#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
424HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
425 pDMA2D_CallbackTypeDef pCallback);
426HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);
427#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
428
432
433
437
438/* IO operation functions *******************************************************/
439HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
440 uint32_t Height);
441HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
442 uint32_t DstAddress, uint32_t Width, uint32_t Height);
443HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
444 uint32_t Height);
445HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
446 uint32_t DstAddress, uint32_t Width, uint32_t Height);
447HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
448HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
449HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
450HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
451HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
452 uint32_t LayerIdx);
453HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
454 uint32_t LayerIdx);
455HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
456HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
457HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
458HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
459HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
460HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
461void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
462void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
463void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
464
468
472
473/* Peripheral Control functions *************************************************/
474HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
475HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
476HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
477HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
478HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
479HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
480
484
488
489/* Peripheral State functions ***************************************************/
490HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d);
491uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d);
492
496
500
501/* Private constants ---------------------------------------------------------*/
502
506
510#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW
514
518#define DMA2D_COLOR_VALUE 0x000000FFU
522
526#define DMA2D_MAX_LAYER 2U
530
534#define DMA2D_BACKGROUND_LAYER 0x00000000U
535#define DMA2D_FOREGROUND_LAYER 0x00000001U
539
543#define DMA2D_OFFSET DMA2D_FGOR_LO
547
551#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U)
552#define DMA2D_LINE DMA2D_NLR_NL
556
560#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U)
564
568
569
570/* Private macros ------------------------------------------------------------*/
574#define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER)\
575 || ((LAYER) == DMA2D_FOREGROUND_LAYER))
576
577#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
578 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
579
580#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || \
581 ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
582 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || \
583 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
584 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
585
586#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
587#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
588#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
589#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
590
591#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || \
592 ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
593 ((INPUT_CM) == DMA2D_INPUT_RGB565) || \
594 ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
595 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || \
596 ((INPUT_CM) == DMA2D_INPUT_L8) || \
597 ((INPUT_CM) == DMA2D_INPUT_AL44) || \
598 ((INPUT_CM) == DMA2D_INPUT_AL88) || \
599 ((INPUT_CM) == DMA2D_INPUT_L4) || \
600 ((INPUT_CM) == DMA2D_INPUT_A8) || \
601 ((INPUT_CM) == DMA2D_INPUT_A4))
602
603#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
604 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
605 ((AlphaMode) == DMA2D_COMBINE_ALPHA))
606
607
608
609
610
611#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
612#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
613#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
614#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
615 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
616 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
617#define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
618 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \
619 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE))
623
627
628#endif /* defined (DMA2D) */
629
633
634#ifdef __cplusplus
635}
636#endif
637
638#endif /* STM32F4xx_HAL_DMA2D_H */
stm32f4xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition stm32f4xx_hal_def.h:39
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition stm32f4xx_hal_def.h:50