STM32F4xx HAL Driver master
STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_hal_dma2d.c
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1
162
163/* Includes ------------------------------------------------------------------*/
164#include "stm32f4xx_hal.h"
165
166#ifdef HAL_DMA2D_MODULE_ENABLED
167#if defined (DMA2D)
168
172
177
178/* Private types -------------------------------------------------------------*/
179/* Private define ------------------------------------------------------------*/
183
187#define DMA2D_TIMEOUT_ABORT (1000U)
188#define DMA2D_TIMEOUT_SUSPEND (1000U)
192
196
197/* Private variables ---------------------------------------------------------*/
198/* Private constants ---------------------------------------------------------*/
199/* Private macro -------------------------------------------------------------*/
200/* Private function prototypes -----------------------------------------------*/
204static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
205 uint32_t Height);
209
210/* Private functions ---------------------------------------------------------*/
211/* Exported functions --------------------------------------------------------*/
215
230
238HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
239{
240 /* Check the DMA2D peripheral state */
241 if (hdma2d == NULL)
242 {
243 return HAL_ERROR;
244 }
245
246 /* Check the parameters */
247 assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
248 assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
249 assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
250 assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
251
252#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
253 if (hdma2d->State == HAL_DMA2D_STATE_RESET)
254 {
255 /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
256 hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
257 hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
258 if (hdma2d->MspInitCallback == NULL)
259 {
260 hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
261 }
262
263 /* Init the low level hardware */
264 hdma2d->MspInitCallback(hdma2d);
265 }
266#else
267 if (hdma2d->State == HAL_DMA2D_STATE_RESET)
268 {
269 /* Allocate lock resource and initialize it */
270 hdma2d->Lock = HAL_UNLOCKED;
271 /* Init the low level hardware */
272 HAL_DMA2D_MspInit(hdma2d);
273 }
274#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
275
276 /* Change DMA2D peripheral state */
277 hdma2d->State = HAL_DMA2D_STATE_BUSY;
278
279 /* DMA2D CR register configuration -------------------------------------------*/
280 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
281
282 /* DMA2D OPFCCR register configuration ---------------------------------------*/
283 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
284
285 /* DMA2D OOR register configuration ------------------------------------------*/
286 MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
287
288
289 /* Update error code */
290 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
291
292 /* Initialize the DMA2D state*/
293 hdma2d->State = HAL_DMA2D_STATE_READY;
294
295 return HAL_OK;
296}
297
305
306HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
307{
308
309 /* Check the DMA2D peripheral state */
310 if (hdma2d == NULL)
311 {
312 return HAL_ERROR;
313 }
314
315 /* Before aborting any DMA2D transfer or CLUT loading, check
316 first whether or not DMA2D clock is enabled */
317 if (__HAL_RCC_DMA2D_IS_CLK_ENABLED() == 1U)
318 {
319 /* Abort DMA2D transfer if any */
320 if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
321 {
322 if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
323 {
324 /* Issue when aborting DMA2D transfer */
325 return HAL_ERROR;
326 }
327 }
328 else
329 {
330 /* Abort background CLUT loading if any */
331 if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
332 {
333 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
334 {
335 /* Issue when aborting background CLUT loading */
336 return HAL_ERROR;
337 }
338 }
339 else
340 {
341 /* Abort foreground CLUT loading if any */
342 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
343 {
344 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
345 {
346 /* Issue when aborting foreground CLUT loading */
347 return HAL_ERROR;
348 }
349 }
350 }
351 }
352 }
353
354 /* Reset DMA2D control registers*/
355 hdma2d->Instance->CR = 0U;
356 hdma2d->Instance->IFCR = 0x3FU;
357 hdma2d->Instance->FGOR = 0U;
358 hdma2d->Instance->BGOR = 0U;
359 hdma2d->Instance->FGPFCCR = 0U;
360 hdma2d->Instance->BGPFCCR = 0U;
361 hdma2d->Instance->OPFCCR = 0U;
362
363#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
364
365 if (hdma2d->MspDeInitCallback == NULL)
366 {
367 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
368 }
369
370 /* DeInit the low level hardware */
371 hdma2d->MspDeInitCallback(hdma2d);
372
373#else
374 /* Carry on with de-initialization of low level hardware */
375 HAL_DMA2D_MspDeInit(hdma2d);
376#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
377
378 /* Update error code */
379 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
380
381 /* Initialize the DMA2D state*/
382 hdma2d->State = HAL_DMA2D_STATE_RESET;
383
384 /* Release Lock */
385 __HAL_UNLOCK(hdma2d);
386
387 return HAL_OK;
388}
389
396__weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef *hdma2d)
397{
398 /* Prevent unused argument(s) compilation warning */
399 UNUSED(hdma2d);
400
401 /* NOTE : This function should not be modified; when the callback is needed,
402 the HAL_DMA2D_MspInit can be implemented in the user file.
403 */
404}
405
412__weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef *hdma2d)
413{
414 /* Prevent unused argument(s) compilation warning */
415 UNUSED(hdma2d);
416
417 /* NOTE : This function should not be modified; when the callback is needed,
418 the HAL_DMA2D_MspDeInit can be implemented in the user file.
419 */
420}
421
422#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
439HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID,
440 pDMA2D_CallbackTypeDef pCallback)
441{
442 HAL_StatusTypeDef status = HAL_OK;
443
444 if (pCallback == NULL)
445 {
446 /* Update the error code */
447 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
448 return HAL_ERROR;
449 }
450 /* Process locked */
451 __HAL_LOCK(hdma2d);
452
453 if (HAL_DMA2D_STATE_READY == hdma2d->State)
454 {
455 switch (CallbackID)
456 {
457 case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
458 hdma2d->XferCpltCallback = pCallback;
459 break;
460
461 case HAL_DMA2D_TRANSFERERROR_CB_ID :
462 hdma2d->XferErrorCallback = pCallback;
463 break;
464
465 case HAL_DMA2D_LINEEVENT_CB_ID :
466 hdma2d->LineEventCallback = pCallback;
467 break;
468
469 case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
470 hdma2d->CLUTLoadingCpltCallback = pCallback;
471 break;
472
473 case HAL_DMA2D_MSPINIT_CB_ID :
474 hdma2d->MspInitCallback = pCallback;
475 break;
476
477 case HAL_DMA2D_MSPDEINIT_CB_ID :
478 hdma2d->MspDeInitCallback = pCallback;
479 break;
480
481 default :
482 /* Update the error code */
483 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
484 /* update return status */
485 status = HAL_ERROR;
486 break;
487 }
488 }
489 else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
490 {
491 switch (CallbackID)
492 {
493 case HAL_DMA2D_MSPINIT_CB_ID :
494 hdma2d->MspInitCallback = pCallback;
495 break;
496
497 case HAL_DMA2D_MSPDEINIT_CB_ID :
498 hdma2d->MspDeInitCallback = pCallback;
499 break;
500
501 default :
502 /* Update the error code */
503 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
504 /* update return status */
505 status = HAL_ERROR;
506 break;
507 }
508 }
509 else
510 {
511 /* Update the error code */
512 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
513 /* update return status */
514 status = HAL_ERROR;
515 }
516
517 /* Release Lock */
518 __HAL_UNLOCK(hdma2d);
519 return status;
520}
521
537HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
538{
539 HAL_StatusTypeDef status = HAL_OK;
540
541 /* Process locked */
542 __HAL_LOCK(hdma2d);
543
544 if (HAL_DMA2D_STATE_READY == hdma2d->State)
545 {
546 switch (CallbackID)
547 {
548 case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
549 hdma2d->XferCpltCallback = NULL;
550 break;
551
552 case HAL_DMA2D_TRANSFERERROR_CB_ID :
553 hdma2d->XferErrorCallback = NULL;
554 break;
555
556 case HAL_DMA2D_LINEEVENT_CB_ID :
557 hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
558 break;
559
560 case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
561 hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
562 break;
563
564 case HAL_DMA2D_MSPINIT_CB_ID :
565 hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */
566 break;
567
568 case HAL_DMA2D_MSPDEINIT_CB_ID :
569 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */
570 break;
571
572 default :
573 /* Update the error code */
574 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
575 /* update return status */
576 status = HAL_ERROR;
577 break;
578 }
579 }
580 else if (HAL_DMA2D_STATE_RESET == hdma2d->State)
581 {
582 switch (CallbackID)
583 {
584 case HAL_DMA2D_MSPINIT_CB_ID :
585 hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (overridden) Msp Init */
586 break;
587
588 case HAL_DMA2D_MSPDEINIT_CB_ID :
589 hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (overridden) Msp DeInit */
590 break;
591
592 default :
593 /* Update the error code */
594 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
595 /* update return status */
596 status = HAL_ERROR;
597 break;
598 }
599 }
600 else
601 {
602 /* Update the error code */
603 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
604 /* update return status */
605 status = HAL_ERROR;
606 }
607
608 /* Release Lock */
609 __HAL_UNLOCK(hdma2d);
610 return status;
611}
612#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
613
617
618
653
668HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
669 uint32_t Height)
670{
671 /* Check the parameters */
672 assert_param(IS_DMA2D_LINE(Height));
673 assert_param(IS_DMA2D_PIXEL(Width));
674
675 /* Process locked */
676 __HAL_LOCK(hdma2d);
677
678 /* Change DMA2D peripheral state */
679 hdma2d->State = HAL_DMA2D_STATE_BUSY;
680
681 /* Configure the source, destination address and the data size */
682 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
683
684 /* Enable the Peripheral */
685 __HAL_DMA2D_ENABLE(hdma2d);
686
687 return HAL_OK;
688}
689
704HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
705 uint32_t Height)
706{
707 /* Check the parameters */
708 assert_param(IS_DMA2D_LINE(Height));
709 assert_param(IS_DMA2D_PIXEL(Width));
710
711 /* Process locked */
712 __HAL_LOCK(hdma2d);
713
714 /* Change DMA2D peripheral state */
715 hdma2d->State = HAL_DMA2D_STATE_BUSY;
716
717 /* Configure the source, destination address and the data size */
718 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
719
720 /* Enable the transfer complete, transfer error and configuration error interrupts */
721 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
722
723 /* Enable the Peripheral */
724 __HAL_DMA2D_ENABLE(hdma2d);
725
726 return HAL_OK;
727}
728
741HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
742 uint32_t DstAddress, uint32_t Width, uint32_t Height)
743{
744 /* Check the parameters */
745 assert_param(IS_DMA2D_LINE(Height));
746 assert_param(IS_DMA2D_PIXEL(Width));
747
748 /* Process locked */
749 __HAL_LOCK(hdma2d);
750
751 /* Change DMA2D peripheral state */
752 hdma2d->State = HAL_DMA2D_STATE_BUSY;
753
754 /* Configure DMA2D Stream source2 address */
755 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
756
757 /* Configure the source, destination address and the data size */
758 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
759
760 /* Enable the Peripheral */
761 __HAL_DMA2D_ENABLE(hdma2d);
762
763 return HAL_OK;
764}
765
778HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2,
779 uint32_t DstAddress, uint32_t Width, uint32_t Height)
780{
781 /* Check the parameters */
782 assert_param(IS_DMA2D_LINE(Height));
783 assert_param(IS_DMA2D_PIXEL(Width));
784
785 /* Process locked */
786 __HAL_LOCK(hdma2d);
787
788 /* Change DMA2D peripheral state */
789 hdma2d->State = HAL_DMA2D_STATE_BUSY;
790
791 /* Configure DMA2D Stream source2 address */
792 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
793
794 /* Configure the source, destination address and the data size */
795 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
796
797 /* Enable the transfer complete, transfer error and configuration error interrupts */
798 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
799
800 /* Enable the Peripheral */
801 __HAL_DMA2D_ENABLE(hdma2d);
802
803 return HAL_OK;
804}
805
812HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
813{
814 uint32_t tickstart;
815
816 /* Abort the DMA2D transfer */
817 /* START bit is reset to make sure not to set it again, in the event the HW clears it
818 between the register read and the register write by the CPU (writing 0 has no
819 effect on START bitvalue) */
820 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
821
822 /* Get tick */
823 tickstart = HAL_GetTick();
824
825 /* Check if the DMA2D is effectively disabled */
826 while ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
827 {
828 if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
829 {
830 /* Update error code */
831 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
832
833 /* Change the DMA2D state */
834 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
835
836 /* Process Unlocked */
837 __HAL_UNLOCK(hdma2d);
838
839 return HAL_TIMEOUT;
840 }
841 }
842
843 /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
844 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC | DMA2D_IT_TE | DMA2D_IT_CE);
845
846 /* Change the DMA2D state*/
847 hdma2d->State = HAL_DMA2D_STATE_READY;
848
849 /* Process Unlocked */
850 __HAL_UNLOCK(hdma2d);
851
852 return HAL_OK;
853}
854
861HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
862{
863 uint32_t tickstart;
864
865 /* Suspend the DMA2D transfer */
866 /* START bit is reset to make sure not to set it again, in the event the HW clears it
867 between the register read and the register write by the CPU (writing 0 has no
868 effect on START bitvalue). */
869 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
870
871 /* Get tick */
872 tickstart = HAL_GetTick();
873
874 /* Check if the DMA2D is effectively suspended */
875 while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
876 {
877 if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
878 {
879 /* Update error code */
880 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
881
882 /* Change the DMA2D state */
883 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
884
885 return HAL_TIMEOUT;
886 }
887 }
888
889 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
890 if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
891 {
892 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
893 }
894 else
895 {
896 /* Make sure SUSP bit is cleared since it is meaningless
897 when no transfer is on-going */
898 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
899 }
900
901 return HAL_OK;
902}
903
910HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
911{
912 /* Check the SUSP and START bits */
913 if ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
914 {
915 /* Ongoing transfer is suspended: change the DMA2D state before resuming */
916 hdma2d->State = HAL_DMA2D_STATE_BUSY;
917 }
918
919 /* Resume the DMA2D transfer */
920 /* START bit is reset to make sure not to set it again, in the event the HW clears it
921 between the register read and the register write by the CPU (writing 0 has no
922 effect on START bitvalue). */
923 CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP | DMA2D_CR_START));
924
925 return HAL_OK;
926}
927
928
938HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
939{
940 /* Check the parameters */
941 assert_param(IS_DMA2D_LAYER(LayerIdx));
942
943 /* Process locked */
944 __HAL_LOCK(hdma2d);
945
946 /* Change DMA2D peripheral state */
947 hdma2d->State = HAL_DMA2D_STATE_BUSY;
948
949 if (LayerIdx == DMA2D_BACKGROUND_LAYER)
950 {
951 /* Enable the background CLUT loading */
952 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
953 }
954 else
955 {
956 /* Enable the foreground CLUT loading */
957 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
958 }
959
960 return HAL_OK;
961}
962
974HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
975 uint32_t LayerIdx)
976{
977 /* Check the parameters */
978 assert_param(IS_DMA2D_LAYER(LayerIdx));
979 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
980 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
981
982 /* Process locked */
983 __HAL_LOCK(hdma2d);
984
985 /* Change DMA2D peripheral state */
986 hdma2d->State = HAL_DMA2D_STATE_BUSY;
987
988 /* Configure the CLUT of the background DMA2D layer */
989 if (LayerIdx == DMA2D_BACKGROUND_LAYER)
990 {
991 /* Write background CLUT memory address */
992 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
993
994 /* Write background CLUT size and CLUT color mode */
995 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
996 ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
997
998 /* Enable the CLUT loading for the background */
999 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1000 }
1001 /* Configure the CLUT of the foreground DMA2D layer */
1002 else
1003 {
1004 /* Write foreground CLUT memory address */
1005 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
1006
1007 /* Write foreground CLUT size and CLUT color mode */
1008 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1009 ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1010
1011 /* Enable the CLUT loading for the foreground */
1012 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1013 }
1014
1015 return HAL_OK;
1016}
1017
1029HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, const DMA2D_CLUTCfgTypeDef *CLUTCfg,
1030 uint32_t LayerIdx)
1031{
1032 /* Check the parameters */
1033 assert_param(IS_DMA2D_LAYER(LayerIdx));
1034 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg->CLUTColorMode));
1035 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg->Size));
1036
1037 /* Process locked */
1038 __HAL_LOCK(hdma2d);
1039
1040 /* Change DMA2D peripheral state */
1041 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1042
1043 /* Configure the CLUT of the background DMA2D layer */
1044 if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1045 {
1046 /* Write background CLUT memory address */
1047 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg->pCLUT);
1048
1049 /* Write background CLUT size and CLUT color mode */
1050 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1051 ((CLUTCfg->Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1052
1053 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1054 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
1055
1056 /* Enable the CLUT loading for the background */
1057 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1058 }
1059 /* Configure the CLUT of the foreground DMA2D layer */
1060 else
1061 {
1062 /* Write foreground CLUT memory address */
1063 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg->pCLUT);
1064
1065 /* Write foreground CLUT size and CLUT color mode */
1066 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1067 ((CLUTCfg->Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg->CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1068
1069 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1070 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
1071
1072 /* Enable the CLUT loading for the foreground */
1073 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1074 }
1075
1076 return HAL_OK;
1077}
1078
1093HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1094{
1095 /* Check the parameters */
1096 assert_param(IS_DMA2D_LAYER(LayerIdx));
1097 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1098 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1099
1100 /* Process locked */
1101 __HAL_LOCK(hdma2d);
1102
1103 /* Change DMA2D peripheral state */
1104 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1105
1106 /* Configure the CLUT of the background DMA2D layer */
1107 if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1108 {
1109 /* Write background CLUT memory address */
1110 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1111
1112 /* Write background CLUT size and CLUT color mode */
1113 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1114 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1115
1116 /* Enable the CLUT loading for the background */
1117 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1118 }
1119 /* Configure the CLUT of the foreground DMA2D layer */
1120 else
1121 {
1122 /* Write foreground CLUT memory address */
1123 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1124
1125 /* Write foreground CLUT size and CLUT color mode */
1126 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1127 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1128
1129 /* Enable the CLUT loading for the foreground */
1130 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1131 }
1132
1133 return HAL_OK;
1134}
1135
1150HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1151{
1152 /* Check the parameters */
1153 assert_param(IS_DMA2D_LAYER(LayerIdx));
1154 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1155 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1156
1157 /* Process locked */
1158 __HAL_LOCK(hdma2d);
1159
1160 /* Change DMA2D peripheral state */
1161 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1162
1163 /* Configure the CLUT of the background DMA2D layer */
1164 if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1165 {
1166 /* Write background CLUT memory address */
1167 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1168
1169 /* Write background CLUT size and CLUT color mode */
1170 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1171 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1172
1173 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1174 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
1175
1176 /* Enable the CLUT loading for the background */
1177 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
1178 }
1179 /* Configure the CLUT of the foreground DMA2D layer */
1180 else
1181 {
1182 /* Write foreground CLUT memory address */
1183 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1184
1185 /* Write foreground CLUT size and CLUT color mode */
1186 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1187 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1188
1189 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
1190 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
1191
1192 /* Enable the CLUT loading for the foreground */
1193 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
1194 }
1195
1196 return HAL_OK;
1197}
1198
1208HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1209{
1210 uint32_t tickstart;
1211 const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
1212
1213 /* Abort the CLUT loading */
1214 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
1215
1216 /* If foreground CLUT loading is considered, update local variables */
1217 if (LayerIdx == DMA2D_FOREGROUND_LAYER)
1218 {
1219 reg = &(hdma2d->Instance->FGPFCCR);
1220 }
1221
1222
1223 /* Get tick */
1224 tickstart = HAL_GetTick();
1225
1226 /* Check if the CLUT loading is aborted */
1227 while ((*reg & DMA2D_BGPFCCR_START) != 0U)
1228 {
1229 if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_ABORT)
1230 {
1231 /* Update error code */
1232 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1233
1234 /* Change the DMA2D state */
1235 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1236
1237 /* Process Unlocked */
1238 __HAL_UNLOCK(hdma2d);
1239
1240 return HAL_TIMEOUT;
1241 }
1242 }
1243
1244 /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
1245 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE | DMA2D_IT_CAE);
1246
1247 /* Change the DMA2D state*/
1248 hdma2d->State = HAL_DMA2D_STATE_READY;
1249
1250 /* Process Unlocked */
1251 __HAL_UNLOCK(hdma2d);
1252
1253 return HAL_OK;
1254}
1255
1265HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1266{
1267 uint32_t tickstart;
1268 uint32_t loadsuspended;
1269 const __IO uint32_t *reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
1270
1271 /* Suspend the CLUT loading */
1272 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1273
1274 /* If foreground CLUT loading is considered, update local variables */
1275 if (LayerIdx == DMA2D_FOREGROUND_LAYER)
1276 {
1277 reg = &(hdma2d->Instance->FGPFCCR);
1278 }
1279
1280 /* Get tick */
1281 tickstart = HAL_GetTick();
1282
1283 /* Check if the CLUT loading is suspended */
1284 /* 1st condition: Suspend Check */
1285 loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
1286 /* 2nd condition: Not Start Check */
1287 loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
1288 while (loadsuspended == 0UL)
1289 {
1290 if ((HAL_GetTick() - tickstart) > DMA2D_TIMEOUT_SUSPEND)
1291 {
1292 /* Update error code */
1293 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1294
1295 /* Change the DMA2D state */
1296 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1297
1298 return HAL_TIMEOUT;
1299 }
1300 /* 1st condition: Suspend Check */
1301 loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP) ? 1UL : 0UL;
1302 /* 2nd condition: Not Start Check */
1303 loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START) ? 1UL : 0UL;
1304 }
1305
1306 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
1307 if ((*reg & DMA2D_BGPFCCR_START) != 0U)
1308 {
1309 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
1310 }
1311 else
1312 {
1313 /* Make sure SUSP bit is cleared since it is meaningless
1314 when no transfer is on-going */
1315 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1316 }
1317
1318 return HAL_OK;
1319}
1320
1330HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1331{
1332 /* Check the SUSP and START bits for background or foreground CLUT loading */
1333 if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1334 {
1335 /* Background CLUT loading suspension check */
1336 if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
1337 {
1338 if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
1339 {
1340 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
1341 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1342 }
1343 }
1344 }
1345 else
1346 {
1347 /* Foreground CLUT loading suspension check */
1348 if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
1349 {
1350 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
1351 {
1352 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
1353 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1354 }
1355 }
1356 }
1357
1358 /* Resume the CLUT loading */
1359 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1360
1361 return HAL_OK;
1362}
1363
1364
1373HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
1374{
1375 uint32_t tickstart;
1376 uint32_t layer_start;
1377 __IO uint32_t isrflags = 0x0U;
1378
1379 /* Polling for DMA2D transfer */
1380 if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
1381 {
1382 /* Get tick */
1383 tickstart = HAL_GetTick();
1384
1385 while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
1386 {
1387 isrflags = READ_REG(hdma2d->Instance->ISR);
1388 if ((isrflags & (DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
1389 {
1390 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1391 {
1392 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1393 }
1394 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1395 {
1396 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1397 }
1398 /* Clear the transfer and configuration error flags */
1399 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1400
1401 /* Change DMA2D state */
1402 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1403
1404 /* Process unlocked */
1405 __HAL_UNLOCK(hdma2d);
1406
1407 return HAL_ERROR;
1408 }
1409 /* Check for the Timeout */
1410 if (Timeout != HAL_MAX_DELAY)
1411 {
1412 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
1413 {
1414 /* Update error code */
1415 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1416
1417 /* Change the DMA2D state */
1418 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1419
1420 /* Process unlocked */
1421 __HAL_UNLOCK(hdma2d);
1422
1423 return HAL_TIMEOUT;
1424 }
1425 }
1426 }
1427 }
1428 /* Polling for CLUT loading (foreground or background) */
1429 layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
1430 layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
1431 if (layer_start != 0U)
1432 {
1433 /* Get tick */
1434 tickstart = HAL_GetTick();
1435
1436 while (__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
1437 {
1438 isrflags = READ_REG(hdma2d->Instance->ISR);
1439 if ((isrflags & (DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE)) != 0U)
1440 {
1441 if ((isrflags & DMA2D_FLAG_CAE) != 0U)
1442 {
1443 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1444 }
1445 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1446 {
1447 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1448 }
1449 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1450 {
1451 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1452 }
1453 /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
1454 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1455
1456 /* Change DMA2D state */
1457 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1458
1459 /* Process unlocked */
1460 __HAL_UNLOCK(hdma2d);
1461
1462 return HAL_ERROR;
1463 }
1464 /* Check for the Timeout */
1465 if (Timeout != HAL_MAX_DELAY)
1466 {
1467 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
1468 {
1469 /* Update error code */
1470 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1471
1472 /* Change the DMA2D state */
1473 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1474
1475 /* Process unlocked */
1476 __HAL_UNLOCK(hdma2d);
1477
1478 return HAL_TIMEOUT;
1479 }
1480 }
1481 }
1482 }
1483
1484 /* Clear the transfer complete and CLUT loading flags */
1485 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC | DMA2D_FLAG_CTC);
1486
1487 /* Change DMA2D state */
1488 hdma2d->State = HAL_DMA2D_STATE_READY;
1489
1490 /* Process unlocked */
1491 __HAL_UNLOCK(hdma2d);
1492
1493 return HAL_OK;
1494}
1501void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
1502{
1503 uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
1504 uint32_t crflags = READ_REG(hdma2d->Instance->CR);
1505
1506 /* Transfer Error Interrupt management ***************************************/
1507 if ((isrflags & DMA2D_FLAG_TE) != 0U)
1508 {
1509 if ((crflags & DMA2D_IT_TE) != 0U)
1510 {
1511 /* Disable the transfer Error interrupt */
1512 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
1513
1514 /* Update error code */
1515 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1516
1517 /* Clear the transfer error flag */
1518 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
1519
1520 /* Change DMA2D state */
1521 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1522
1523 /* Process Unlocked */
1524 __HAL_UNLOCK(hdma2d);
1525
1526 if (hdma2d->XferErrorCallback != NULL)
1527 {
1528 /* Transfer error Callback */
1529 hdma2d->XferErrorCallback(hdma2d);
1530 }
1531 }
1532 }
1533 /* Configuration Error Interrupt management **********************************/
1534 if ((isrflags & DMA2D_FLAG_CE) != 0U)
1535 {
1536 if ((crflags & DMA2D_IT_CE) != 0U)
1537 {
1538 /* Disable the Configuration Error interrupt */
1539 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
1540
1541 /* Clear the Configuration error flag */
1542 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
1543
1544 /* Update error code */
1545 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1546
1547 /* Change DMA2D state */
1548 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1549
1550 /* Process Unlocked */
1551 __HAL_UNLOCK(hdma2d);
1552
1553 if (hdma2d->XferErrorCallback != NULL)
1554 {
1555 /* Transfer error Callback */
1556 hdma2d->XferErrorCallback(hdma2d);
1557 }
1558 }
1559 }
1560 /* CLUT access Error Interrupt management ***********************************/
1561 if ((isrflags & DMA2D_FLAG_CAE) != 0U)
1562 {
1563 if ((crflags & DMA2D_IT_CAE) != 0U)
1564 {
1565 /* Disable the CLUT access error interrupt */
1566 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
1567
1568 /* Clear the CLUT access error flag */
1569 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
1570
1571 /* Update error code */
1572 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1573
1574 /* Change DMA2D state */
1575 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1576
1577 /* Process Unlocked */
1578 __HAL_UNLOCK(hdma2d);
1579
1580 if (hdma2d->XferErrorCallback != NULL)
1581 {
1582 /* Transfer error Callback */
1583 hdma2d->XferErrorCallback(hdma2d);
1584 }
1585 }
1586 }
1587 /* Transfer watermark Interrupt management **********************************/
1588 if ((isrflags & DMA2D_FLAG_TW) != 0U)
1589 {
1590 if ((crflags & DMA2D_IT_TW) != 0U)
1591 {
1592 /* Disable the transfer watermark interrupt */
1593 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
1594
1595 /* Clear the transfer watermark flag */
1596 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
1597
1598 /* Transfer watermark Callback */
1599#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
1600 hdma2d->LineEventCallback(hdma2d);
1601#else
1602 HAL_DMA2D_LineEventCallback(hdma2d);
1603#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
1604
1605 }
1606 }
1607 /* Transfer Complete Interrupt management ************************************/
1608 if ((isrflags & DMA2D_FLAG_TC) != 0U)
1609 {
1610 if ((crflags & DMA2D_IT_TC) != 0U)
1611 {
1612 /* Disable the transfer complete interrupt */
1613 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
1614
1615 /* Clear the transfer complete flag */
1616 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
1617
1618 /* Update error code */
1619 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1620
1621 /* Change DMA2D state */
1622 hdma2d->State = HAL_DMA2D_STATE_READY;
1623
1624 /* Process Unlocked */
1625 __HAL_UNLOCK(hdma2d);
1626
1627 if (hdma2d->XferCpltCallback != NULL)
1628 {
1629 /* Transfer complete Callback */
1630 hdma2d->XferCpltCallback(hdma2d);
1631 }
1632 }
1633 }
1634 /* CLUT Transfer Complete Interrupt management ******************************/
1635 if ((isrflags & DMA2D_FLAG_CTC) != 0U)
1636 {
1637 if ((crflags & DMA2D_IT_CTC) != 0U)
1638 {
1639 /* Disable the CLUT transfer complete interrupt */
1640 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
1641
1642 /* Clear the CLUT transfer complete flag */
1643 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
1644
1645 /* Update error code */
1646 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1647
1648 /* Change DMA2D state */
1649 hdma2d->State = HAL_DMA2D_STATE_READY;
1650
1651 /* Process Unlocked */
1652 __HAL_UNLOCK(hdma2d);
1653
1654 /* CLUT Transfer complete Callback */
1655#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
1656 hdma2d->CLUTLoadingCpltCallback(hdma2d);
1657#else
1658 HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
1659#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
1660 }
1661 }
1662
1663}
1664
1671__weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
1672{
1673 /* Prevent unused argument(s) compilation warning */
1674 UNUSED(hdma2d);
1675
1676 /* NOTE : This function should not be modified; when the callback is needed,
1677 the HAL_DMA2D_LineEventCallback can be implemented in the user file.
1678 */
1679}
1680
1687__weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
1688{
1689 /* Prevent unused argument(s) compilation warning */
1690 UNUSED(hdma2d);
1691
1692 /* NOTE : This function should not be modified; when the callback is needed,
1693 the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
1694 */
1695}
1696
1700
1719
1730HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1731{
1732 const DMA2D_LayerCfgTypeDef *pLayerCfg;
1733 uint32_t regMask;
1734 uint32_t regValue;
1735
1736 /* Check the parameters */
1737 assert_param(IS_DMA2D_LAYER(LayerIdx));
1738 assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
1739 if (hdma2d->Init.Mode != DMA2D_R2M)
1740 {
1741 assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
1742 if (hdma2d->Init.Mode != DMA2D_M2M)
1743 {
1744 assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
1745 }
1746 }
1747
1748 /* Process locked */
1749 __HAL_LOCK(hdma2d);
1750
1751 /* Change DMA2D peripheral state */
1752 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1753
1754 pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
1755
1756 /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
1757 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);
1758 regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
1759
1760
1761 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1762 {
1763 regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
1764 }
1765 else
1766 {
1767 regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
1768 }
1769
1770 /* Configure the background DMA2D layer */
1771 if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1772 {
1773 /* Write DMA2D BGPFCCR register */
1774 MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
1775
1776 /* DMA2D BGOR register configuration -------------------------------------*/
1777 WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
1778
1779 /* DMA2D BGCOLR register configuration -------------------------------------*/
1780 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1781 {
1782 WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE | DMA2D_BGCOLR_GREEN | \
1783 DMA2D_BGCOLR_RED));
1784 }
1785 }
1786 /* Configure the foreground DMA2D layer */
1787 else
1788 {
1789
1790
1791 /* Write DMA2D FGPFCCR register */
1792 MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
1793
1794 /* DMA2D FGOR register configuration -------------------------------------*/
1795 WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
1796
1797 /* DMA2D FGCOLR register configuration -------------------------------------*/
1798 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1799 {
1800 WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE | DMA2D_FGCOLR_GREEN | \
1801 DMA2D_FGCOLR_RED));
1802 }
1803 }
1804 /* Initialize the DMA2D state*/
1805 hdma2d->State = HAL_DMA2D_STATE_READY;
1806
1807 /* Process unlocked */
1808 __HAL_UNLOCK(hdma2d);
1809
1810 return HAL_OK;
1811}
1812
1827HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1828{
1829 /* Check the parameters */
1830 assert_param(IS_DMA2D_LAYER(LayerIdx));
1831 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1832 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1833
1834 /* Process locked */
1835 __HAL_LOCK(hdma2d);
1836
1837 /* Change DMA2D peripheral state */
1838 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1839
1840 /* Configure the CLUT of the background DMA2D layer */
1841 if (LayerIdx == DMA2D_BACKGROUND_LAYER)
1842 {
1843 /* Write background CLUT memory address */
1844 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1845
1846 /* Write background CLUT size and CLUT color mode */
1847 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1848 ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
1849 }
1850 /* Configure the CLUT of the foreground DMA2D layer */
1851 else
1852 {
1853 /* Write foreground CLUT memory address */
1854 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1855
1856 /* Write foreground CLUT size and CLUT color mode */
1857 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1858 ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
1859 }
1860
1861 /* Set the DMA2D state to Ready*/
1862 hdma2d->State = HAL_DMA2D_STATE_READY;
1863
1864 /* Process unlocked */
1865 __HAL_UNLOCK(hdma2d);
1866
1867 return HAL_OK;
1868}
1869
1870
1880
1881HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
1882{
1883 /* Check the parameters */
1884 if (Line > DMA2D_LWR_LW)
1885 {
1886 return HAL_ERROR;
1887 }
1888 else
1889 {
1890 /* Process locked */
1891 __HAL_LOCK(hdma2d);
1892
1893 /* Change DMA2D peripheral state */
1894 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1895
1896 /* Sets the Line watermark configuration */
1897 WRITE_REG(hdma2d->Instance->LWR, Line);
1898
1899 /* Enable the Line interrupt */
1900 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
1901
1902 /* Initialize the DMA2D state*/
1903 hdma2d->State = HAL_DMA2D_STATE_READY;
1904
1905 /* Process unlocked */
1906 __HAL_UNLOCK(hdma2d);
1907
1908 return HAL_OK;
1909 }
1910}
1911
1917HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1918{
1919 /* Process Locked */
1920 __HAL_LOCK(hdma2d);
1921
1922 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1923
1924 /* Set DMA2D_AMTCR EN bit */
1925 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1926
1927 hdma2d->State = HAL_DMA2D_STATE_READY;
1928
1929 /* Process Unlocked */
1930 __HAL_UNLOCK(hdma2d);
1931
1932 return HAL_OK;
1933}
1934
1940HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1941{
1942 /* Process Locked */
1943 __HAL_LOCK(hdma2d);
1944
1945 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1946
1947 /* Clear DMA2D_AMTCR EN bit */
1948 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1949
1950 hdma2d->State = HAL_DMA2D_STATE_READY;
1951
1952 /* Process Unlocked */
1953 __HAL_UNLOCK(hdma2d);
1954
1955 return HAL_OK;
1956}
1957
1966HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
1967{
1968 /* Process Locked */
1969 __HAL_LOCK(hdma2d);
1970
1971 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1972
1973 /* Set DMA2D_AMTCR DT field */
1974 MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));
1975
1976 hdma2d->State = HAL_DMA2D_STATE_READY;
1977
1978 /* Process Unlocked */
1979 __HAL_UNLOCK(hdma2d);
1980
1981 return HAL_OK;
1982}
1983
1987
1988
2004
2011HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(const DMA2D_HandleTypeDef *hdma2d)
2012{
2013 return hdma2d->State;
2014}
2015
2022uint32_t HAL_DMA2D_GetError(const DMA2D_HandleTypeDef *hdma2d)
2023{
2024 return hdma2d->ErrorCode;
2025}
2026
2030
2034
2035
2039
2050static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,
2051 uint32_t Height)
2052{
2053 uint32_t tmp;
2054 uint32_t tmp1;
2055 uint32_t tmp2;
2056 uint32_t tmp3;
2057 uint32_t tmp4;
2058
2059 /* Configure DMA2D data size */
2060 MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL | DMA2D_NLR_PL), (Height | (Width << DMA2D_NLR_PL_Pos)));
2061
2062 /* Configure DMA2D destination address */
2063 WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
2064
2065 /* Register to memory DMA2D mode selected */
2066 if (hdma2d->Init.Mode == DMA2D_R2M)
2067 {
2068 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
2069 tmp2 = pdata & DMA2D_OCOLR_RED_1;
2070 tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
2071 tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
2072
2073 /* Prepare the value to be written to the OCOLR register according to the color mode */
2074 if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
2075 {
2076 tmp = (tmp3 | tmp2 | tmp1 | tmp4);
2077 }
2078 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
2079 {
2080 tmp = (tmp3 | tmp2 | tmp4);
2081 }
2082 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
2083 {
2084 tmp2 = (tmp2 >> 19U);
2085 tmp3 = (tmp3 >> 10U);
2086 tmp4 = (tmp4 >> 3U);
2087 tmp = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
2088 }
2089 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
2090 {
2091 tmp1 = (tmp1 >> 31U);
2092 tmp2 = (tmp2 >> 19U);
2093 tmp3 = (tmp3 >> 11U);
2094 tmp4 = (tmp4 >> 3U);
2095 tmp = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
2096 }
2097 else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
2098 {
2099 tmp1 = (tmp1 >> 28U);
2100 tmp2 = (tmp2 >> 20U);
2101 tmp3 = (tmp3 >> 12U);
2102 tmp4 = (tmp4 >> 4U);
2103 tmp = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
2104 }
2105 /* Write to DMA2D OCOLR register */
2106 WRITE_REG(hdma2d->Instance->OCOLR, tmp);
2107 }
2108 else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
2109 {
2110 /* Configure DMA2D source address */
2111 WRITE_REG(hdma2d->Instance->FGMAR, pdata);
2112 }
2113}
2114
2118
2122
2126#endif /* DMA2D */
2127#endif /* HAL_DMA2D_MODULE_ENABLED */
HAL_GetTick
uint32_t HAL_GetTick(void)
Provides a tick value in millisecond.
Definition stm32f4xx_hal.c:323
assert_param
#define assert_param(expr)
Definition stm32_assert_template.h:46
stm32f4xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition stm32f4xx_hal_def.h:39
HAL_TIMEOUT
@ HAL_TIMEOUT
Definition stm32f4xx_hal_def.h:43
HAL_ERROR
@ HAL_ERROR
Definition stm32f4xx_hal_def.h:41
HAL_OK
@ HAL_OK
Definition stm32f4xx_hal_def.h:40
__HAL_UNLOCK
#define __HAL_UNLOCK(__HANDLE__)
Definition stm32f4xx_hal_def.h:105
HAL_MAX_DELAY
#define HAL_MAX_DELAY
Definition stm32f4xx_hal_def.h:61
HAL_UNLOCKED
@ HAL_UNLOCKED
Definition stm32f4xx_hal_def.h:51
__HAL_LOCK
#define __HAL_LOCK(__HANDLE__)
Definition stm32f4xx_hal_def.h:93