STM32F4xx HAL Driver master
STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_hal_cryp.c
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1
257
258/* Includes ------------------------------------------------------------------*/
259#include "stm32f4xx_hal.h"
260
264
265#if defined (AES) || defined (CRYP)
266
271
272
273#ifdef HAL_CRYP_MODULE_ENABLED
274
275/* Private typedef -----------------------------------------------------------*/
276/* Private define ------------------------------------------------------------*/
280#define CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/
281#define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is
282 299 clock cycles.*/
283#define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
284
285#define CRYP_PHASE_READY 0x00000001U
286#define CRYP_PHASE_PROCESS 0x00000002U
287
288#if defined(AES)
289#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
290#define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0
291#define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1
292#define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE
293#define CRYP_PHASE_INIT 0x00000000U
294#define CRYP_PHASE_HEADER AES_CR_GCMPH_0
295#define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1
296#define CRYP_PHASE_FINAL AES_CR_GCMPH
297#else /* CRYP */
298#define CRYP_PHASE_INIT 0x00000000U
299#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
300#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
301#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
302#define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U
303#define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR
304#endif /* End CRYP or AES */
305
306/* CTR1 information to use in CCM algorithm */
307#define CRYP_CCM_CTR1_0 0x07FFFFFFU
308#define CRYP_CCM_CTR1_1 0xFFFFFF00U
309#define CRYP_CCM_CTR1_2 0x00000001U
310
311
315
316
317/* Private macro -------------------------------------------------------------*/
321
322#if defined(CRYP)
323
324#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
325 (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
326 }while(0)
327
328#define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
329
330#else /*AES*/
331#define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
332 (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
333 }while(0)
334#endif /* End AES or CRYP*/
335
336
340
341/* Private struct -------------------------------------------------------------*/
342/* Private variables ---------------------------------------------------------*/
343/* Private function prototypes -----------------------------------------------*/
347
348static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
349static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
350static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
351static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
352static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
353static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
354#if defined (CRYP_CR_ALGOMODE_AES_GCM)|| defined (AES)
355static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
356static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
357static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
358static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
359static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
360static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
361static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
362static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
363static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
364static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
365static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
366#endif /* AES or GCM CCM defined*/
367static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
368static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
369static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
370static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
371static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
372static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
373#if defined (CRYP)
374static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp);
375#if defined (CRYP_CR_ALGOMODE_AES_GCM)
376static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
377#endif /* GCM CCM defined*/
378static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
379static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
380static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
381#else /*AES*/
382static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
383#endif /* End CRYP or AES */
384
388
389/* Exported functions ---------------------------------------------------------*/
390
394
395
423
424
432HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
433{
434 /* Check the CRYP handle allocation */
435 if (hcryp == NULL)
436 {
437 return HAL_ERROR;
438 }
439
440 /* Check parameters */
441 assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
442 assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
443 assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
444 assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
445
446#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
447 if (hcryp->State == HAL_CRYP_STATE_RESET)
448 {
449 /* Allocate lock resource and initialize it */
450 hcryp->Lock = HAL_UNLOCKED;
451
452 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
453 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
454 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
455
456 if (hcryp->MspInitCallback == NULL)
457 {
458 hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */
459 }
460
461 /* Init the low level hardware */
462 hcryp->MspInitCallback(hcryp);
463 }
464#else
465 if (hcryp->State == HAL_CRYP_STATE_RESET)
466 {
467 /* Allocate lock resource and initialize it */
468 hcryp->Lock = HAL_UNLOCKED;
469
470 /* Init the low level hardware */
471 HAL_CRYP_MspInit(hcryp);
472 }
473#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
474
475 /* Set the key size(This bit field is don't care in the DES or TDES modes) data type and Algorithm */
476#if defined (CRYP)
477
478 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
479 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
480
481#else /*AES*/
482
483 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
484 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
485
486#endif /* End AES or CRYP*/
487
488 /* Reset Error Code field */
489 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
490
491 /* Change the CRYP state */
492 hcryp->State = HAL_CRYP_STATE_READY;
493
494 /* Set the default CRYP phase */
495 hcryp->Phase = CRYP_PHASE_READY;
496
497 /* Return function status */
498 return HAL_OK;
499}
500
507HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
508{
509 /* Check the CRYP handle allocation */
510 if (hcryp == NULL)
511 {
512 return HAL_ERROR;
513 }
514
515 /* Set the default CRYP phase */
516 hcryp->Phase = CRYP_PHASE_READY;
517
518 /* Reset CrypInCount and CrypOutCount */
519 hcryp->CrypInCount = 0;
520 hcryp->CrypOutCount = 0;
521 hcryp->CrypHeaderCount = 0;
522
523 /* Disable the CRYP peripheral clock */
524 __HAL_CRYP_DISABLE(hcryp);
525
526#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
527
528 if (hcryp->MspDeInitCallback == NULL)
529 {
530 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */
531 }
532 /* DeInit the low level hardware */
533 hcryp->MspDeInitCallback(hcryp);
534
535#else
536
537 /* DeInit the low level hardware: CLOCK, NVIC.*/
538 HAL_CRYP_MspDeInit(hcryp);
539
540#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
541
542 /* Change the CRYP state */
543 hcryp->State = HAL_CRYP_STATE_RESET;
544
545 /* Release Lock */
546 __HAL_UNLOCK(hcryp);
547
548 /* Return function status */
549 return HAL_OK;
550}
551
560HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
561{
562 /* Check the CRYP handle allocation */
563 if ((hcryp == NULL) || (pConf == NULL))
564 {
565 return HAL_ERROR;
566 }
567
568 /* Check parameters */
569 assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
570 assert_param(IS_CRYP_DATATYPE(pConf->DataType));
571 assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
572
573 if (hcryp->State == HAL_CRYP_STATE_READY)
574 {
575 /* Change the CRYP state */
576 hcryp->State = HAL_CRYP_STATE_BUSY;
577
578 /* Process locked */
579 __HAL_LOCK(hcryp);
580
581 /* Set CRYP parameters */
582 hcryp->Init.DataType = pConf->DataType;
583 hcryp->Init.pKey = pConf->pKey;
584 hcryp->Init.Algorithm = pConf->Algorithm;
585 hcryp->Init.KeySize = pConf->KeySize;
586 hcryp->Init.pInitVect = pConf->pInitVect;
587 hcryp->Init.Header = pConf->Header;
588 hcryp->Init.HeaderSize = pConf->HeaderSize;
589 hcryp->Init.B0 = pConf->B0;
590 hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
591 hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
592 hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
593
594 /* Set the key size(This bit field is don't care in the DES or TDES modes) data type, AlgoMode and operating mode*/
595#if defined (CRYP)
596
597 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
598 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
599
600#else /*AES*/
601 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
602 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
603
604 /*clear error flags*/
605 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR);
606
607#endif /* End AES or CRYP */
608
609 /* Process Unlocked */
610 __HAL_UNLOCK(hcryp);
611
612 /* Reset Error Code field */
613 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
614
615 /* Change the CRYP state */
616 hcryp->State = HAL_CRYP_STATE_READY;
617
618 /* Set the default CRYP phase */
619 hcryp->Phase = CRYP_PHASE_READY;
620
621 /* Return function status */
622 return HAL_OK;
623 }
624 else
625 {
626 /* Process Unlocked */
627 __HAL_UNLOCK(hcryp);
628
629 /* Busy error code field */
630 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
631 return HAL_ERROR;
632 }
633}
634
642HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
643{
644 /* Check the CRYP handle allocation */
645 if ((hcryp == NULL) || (pConf == NULL))
646 {
647 return HAL_ERROR;
648 }
649
650 if (hcryp->State == HAL_CRYP_STATE_READY)
651 {
652 /* Change the CRYP state */
653 hcryp->State = HAL_CRYP_STATE_BUSY;
654
655 /* Process locked */
656 __HAL_LOCK(hcryp);
657
658 /* Get CRYP parameters */
659 pConf->DataType = hcryp->Init.DataType;
660 pConf->pKey = hcryp->Init.pKey;
661 pConf->Algorithm = hcryp->Init.Algorithm;
662 pConf->KeySize = hcryp->Init.KeySize ;
663 pConf->pInitVect = hcryp->Init.pInitVect;
664 pConf->Header = hcryp->Init.Header ;
665 pConf->HeaderSize = hcryp->Init.HeaderSize;
666 pConf->B0 = hcryp->Init.B0;
667 pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
668 pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
669 pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
670
671 /* Process Unlocked */
672 __HAL_UNLOCK(hcryp);
673
674 /* Change the CRYP state */
675 hcryp->State = HAL_CRYP_STATE_READY;
676
677 /* Return function status */
678 return HAL_OK;
679 }
680 else
681 {
682 /* Process Unlocked */
683 __HAL_UNLOCK(hcryp);
684
685 /* Busy error code field */
686 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
687 return HAL_ERROR;
688 }
689}
696__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
697{
698 /* Prevent unused argument(s) compilation warning */
699 UNUSED(hcryp);
700
701 /* NOTE : This function should not be modified, when the callback is needed,
702 the HAL_CRYP_MspInit can be implemented in the user file
703 */
704}
705
712__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
713{
714 /* Prevent unused argument(s) compilation warning */
715 UNUSED(hcryp);
716
717 /* NOTE : This function should not be modified, when the callback is needed,
718 the HAL_CRYP_MspDeInit can be implemented in the user file
719 */
720}
721
722#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
737HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
738 pCRYP_CallbackTypeDef pCallback)
739{
740 HAL_StatusTypeDef status = HAL_OK;
741
742 if (pCallback == NULL)
743 {
744 /* Update the error code */
745 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
746
747 return HAL_ERROR;
748 }
749 /* Process locked */
750 __HAL_LOCK(hcryp);
751
752 if (hcryp->State == HAL_CRYP_STATE_READY)
753 {
754 switch (CallbackID)
755 {
756 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
757 hcryp->InCpltCallback = pCallback;
758 break;
759
760 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
761 hcryp->OutCpltCallback = pCallback;
762 break;
763
764 case HAL_CRYP_ERROR_CB_ID :
765 hcryp->ErrorCallback = pCallback;
766 break;
767
768 case HAL_CRYP_MSPINIT_CB_ID :
769 hcryp->MspInitCallback = pCallback;
770 break;
771
772 case HAL_CRYP_MSPDEINIT_CB_ID :
773 hcryp->MspDeInitCallback = pCallback;
774 break;
775
776 default :
777 /* Update the error code */
778 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
779 /* Return error status */
780 status = HAL_ERROR;
781 break;
782 }
783 }
784 else if (hcryp->State == HAL_CRYP_STATE_RESET)
785 {
786 switch (CallbackID)
787 {
788 case HAL_CRYP_MSPINIT_CB_ID :
789 hcryp->MspInitCallback = pCallback;
790 break;
791
792 case HAL_CRYP_MSPDEINIT_CB_ID :
793 hcryp->MspDeInitCallback = pCallback;
794 break;
795
796 default :
797 /* Update the error code */
798 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
799 /* Return error status */
800 status = HAL_ERROR;
801 break;
802 }
803 }
804 else
805 {
806 /* Update the error code */
807 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
808 /* Return error status */
809 status = HAL_ERROR;
810 }
811
812 /* Release Lock */
813 __HAL_UNLOCK(hcryp);
814
815 return status;
816}
817
831HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
832{
833 HAL_StatusTypeDef status = HAL_OK;
834
835 /* Process locked */
836 __HAL_LOCK(hcryp);
837
838 if (hcryp->State == HAL_CRYP_STATE_READY)
839 {
840 switch (CallbackID)
841 {
842 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
843 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
844 break;
845
846 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
847 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
848 break;
849
850 case HAL_CRYP_ERROR_CB_ID :
851 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
852 break;
853
854 case HAL_CRYP_MSPINIT_CB_ID :
855 hcryp->MspInitCallback = HAL_CRYP_MspInit;
856 break;
857
858 case HAL_CRYP_MSPDEINIT_CB_ID :
859 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
860 break;
861
862 default :
863 /* Update the error code */
864 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
865 /* Return error status */
866 status = HAL_ERROR;
867 break;
868 }
869 }
870 else if (hcryp->State == HAL_CRYP_STATE_RESET)
871 {
872 switch (CallbackID)
873 {
874 case HAL_CRYP_MSPINIT_CB_ID :
875 hcryp->MspInitCallback = HAL_CRYP_MspInit;
876 break;
877
878 case HAL_CRYP_MSPDEINIT_CB_ID :
879 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
880 break;
881
882 default :
883 /* Update the error code */
884 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
885 /* Return error status */
886 status = HAL_ERROR;
887 break;
888 }
889 }
890 else
891 {
892 /* Update the error code */
893 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
894 /* Return error status */
895 status = HAL_ERROR;
896 }
897
898 /* Release Lock */
899 __HAL_UNLOCK(hcryp);
900
901 return status;
902}
903#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
907
936
937
948HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
949 uint32_t Timeout)
950{
951 uint32_t algo;
952 HAL_StatusTypeDef status;
953
954 if (hcryp->State == HAL_CRYP_STATE_READY)
955 {
956 /* Change state Busy */
957 hcryp->State = HAL_CRYP_STATE_BUSY;
958
959 /* Process locked */
960 __HAL_LOCK(hcryp);
961
962 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
963 hcryp->CrypInCount = 0U;
964 hcryp->CrypOutCount = 0U;
965 hcryp->pCrypInBuffPtr = Input;
966 hcryp->pCrypOutBuffPtr = Output;
967
968 /* Calculate Size parameter in Byte*/
969 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
970 {
971 hcryp->Size = Size * 4U;
972 }
973 else
974 {
975 hcryp->Size = Size;
976 }
977
978#if defined (CRYP)
979 /* Set Encryption operating mode*/
980 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
981
982 /* algo get algorithm selected */
983 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
984
985 switch (algo)
986 {
987 case CRYP_DES_ECB:
988 case CRYP_DES_CBC:
989 case CRYP_TDES_ECB:
990 case CRYP_TDES_CBC:
991
992 /*Set Key */
993 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
994 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
995 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
996 {
997 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
998 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
999 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1000 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1001 }
1002
1003 /*Set Initialization Vector (IV)*/
1004 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1005 {
1006 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1007 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1008 }
1009
1010 /* Flush FIFO */
1011 HAL_CRYP_FIFO_FLUSH(hcryp);
1012
1013 /* Set the phase */
1014 hcryp->Phase = CRYP_PHASE_PROCESS;
1015
1016 /* Start DES/TDES encryption process */
1017 status = CRYP_TDES_Process(hcryp, Timeout);
1018 break;
1019
1020 case CRYP_AES_ECB:
1021 case CRYP_AES_CBC:
1022 case CRYP_AES_CTR:
1023
1024 /* AES encryption */
1025 status = CRYP_AES_Encrypt(hcryp, Timeout);
1026 break;
1027#if defined (CRYP_CR_ALGOMODE_AES_GCM)
1028 case CRYP_AES_GCM:
1029
1030 /* AES GCM encryption */
1031 status = CRYP_AESGCM_Process(hcryp, Timeout);
1032
1033 break;
1034
1035 case CRYP_AES_CCM:
1036
1037 /* AES CCM encryption */
1038 status = CRYP_AESCCM_Process(hcryp, Timeout);
1039 break;
1040#endif /* GCM CCM defined*/
1041 default:
1042 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1043 /* Change the CRYP peripheral state */
1044 hcryp->State = HAL_CRYP_STATE_READY;
1045 /* Process unlocked */
1046 __HAL_UNLOCK(hcryp);
1047 return HAL_ERROR;
1048 }
1049
1050#else /*AES*/
1051
1052 /* Set the operating mode*/
1053 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1054
1055 /* algo get algorithm selected */
1056 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1057
1058 switch (algo)
1059 {
1060
1061 case CRYP_AES_ECB:
1062 case CRYP_AES_CBC:
1063 case CRYP_AES_CTR:
1064
1065 /* AES encryption */
1066 status = CRYP_AES_Encrypt(hcryp, Timeout);
1067 break;
1068
1069 case CRYP_AES_GCM_GMAC:
1070
1071 /* AES GCM encryption */
1072 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1073 break;
1074
1075 case CRYP_AES_CCM:
1076
1077 /* AES CCM encryption */
1078 status = CRYP_AESCCM_Process(hcryp, Timeout);
1079 break;
1080
1081 default:
1082 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1083 /* Change the CRYP peripheral state */
1084 hcryp->State = HAL_CRYP_STATE_READY;
1085 /* Process unlocked */
1086 __HAL_UNLOCK(hcryp);
1087 return HAL_ERROR;
1088 }
1089#endif /*end AES or CRYP */
1090
1091 if (status == HAL_OK)
1092 {
1093 /* Change the CRYP peripheral state */
1094 hcryp->State = HAL_CRYP_STATE_READY;
1095
1096 /* Process unlocked */
1097 __HAL_UNLOCK(hcryp);
1098 }
1099 }
1100 else
1101 {
1102 /* Busy error code field */
1103 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1104 return HAL_ERROR;
1105 }
1106
1107 /* Return function status */
1108 return HAL_OK;
1109}
1110
1121HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
1122 uint32_t Timeout)
1123{
1124 HAL_StatusTypeDef status;
1125 uint32_t algo;
1126
1127 if (hcryp->State == HAL_CRYP_STATE_READY)
1128 {
1129 /* Change state Busy */
1130 hcryp->State = HAL_CRYP_STATE_BUSY;
1131
1132 /* Process locked */
1133 __HAL_LOCK(hcryp);
1134
1135 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1136 hcryp->CrypInCount = 0U;
1137 hcryp->CrypOutCount = 0U;
1138 hcryp->pCrypInBuffPtr = Input;
1139 hcryp->pCrypOutBuffPtr = Output;
1140
1141 /* Calculate Size parameter in Byte*/
1142 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1143 {
1144 hcryp->Size = Size * 4U;
1145 }
1146 else
1147 {
1148 hcryp->Size = Size;
1149 }
1150
1151#if defined (CRYP)
1152
1153 /* Set Decryption operating mode*/
1154 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1155
1156 /* algo get algorithm selected */
1157 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1158
1159 switch (algo)
1160 {
1161 case CRYP_DES_ECB:
1162 case CRYP_DES_CBC:
1163 case CRYP_TDES_ECB:
1164 case CRYP_TDES_CBC:
1165
1166 /*Set Key */
1167 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1168 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1169 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1170 {
1171 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1172 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1173 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1174 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1175 }
1176
1177 /*Set Initialization Vector (IV)*/
1178 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1179 {
1180 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1181 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1182 }
1183
1184 /* Flush FIFO */
1185 HAL_CRYP_FIFO_FLUSH(hcryp);
1186
1187 /* Set the phase */
1188 hcryp->Phase = CRYP_PHASE_PROCESS;
1189
1190 /* Start DES/TDES decryption process */
1191 status = CRYP_TDES_Process(hcryp, Timeout);
1192
1193 break;
1194
1195 case CRYP_AES_ECB:
1196 case CRYP_AES_CBC:
1197 case CRYP_AES_CTR:
1198
1199 /* AES decryption */
1200 status = CRYP_AES_Decrypt(hcryp, Timeout);
1201 break;
1202#if defined (CRYP_CR_ALGOMODE_AES_GCM)
1203 case CRYP_AES_GCM:
1204
1205 /* AES GCM decryption */
1206 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1207 break;
1208
1209 case CRYP_AES_CCM:
1210
1211 /* AES CCM decryption */
1212 status = CRYP_AESCCM_Process(hcryp, Timeout);
1213 break;
1214#endif /* GCM CCM defined*/
1215 default:
1216 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1217 /* Change the CRYP peripheral state */
1218 hcryp->State = HAL_CRYP_STATE_READY;
1219 /* Process unlocked */
1220 __HAL_UNLOCK(hcryp);
1221 return HAL_ERROR;
1222 }
1223
1224#else /*AES*/
1225
1226 /* Set Decryption operating mode*/
1227 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1228
1229 /* algo get algorithm selected */
1230 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1231
1232 switch (algo)
1233 {
1234
1235 case CRYP_AES_ECB:
1236 case CRYP_AES_CBC:
1237 case CRYP_AES_CTR:
1238
1239 /* AES decryption */
1240 status = CRYP_AES_Decrypt(hcryp, Timeout);
1241 break;
1242
1243 case CRYP_AES_GCM_GMAC:
1244
1245 /* AES GCM decryption */
1246 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1247 break;
1248
1249 case CRYP_AES_CCM:
1250
1251 /* AES CCM decryption */
1252 status = CRYP_AESCCM_Process(hcryp, Timeout);
1253 break;
1254
1255 default:
1256 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1257 /* Change the CRYP peripheral state */
1258 hcryp->State = HAL_CRYP_STATE_READY;
1259 /* Process unlocked */
1260 __HAL_UNLOCK(hcryp);
1261 return HAL_ERROR;
1262 }
1263#endif /* End AES or CRYP */
1264
1265 if (status == HAL_OK)
1266 {
1267 /* Change the CRYP peripheral state */
1268 hcryp->State = HAL_CRYP_STATE_READY;
1269
1270 /* Process unlocked */
1271 __HAL_UNLOCK(hcryp);
1272 }
1273 }
1274 else
1275 {
1276 /* Busy error code field */
1277 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1278 return HAL_ERROR;
1279 }
1280
1281 /* Return function status */
1282 return HAL_OK;
1283}
1284
1294HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1295{
1296 uint32_t algo;
1297 HAL_StatusTypeDef status = HAL_OK;
1298
1299 if (hcryp->State == HAL_CRYP_STATE_READY)
1300 {
1301 /* Change state Busy */
1302 hcryp->State = HAL_CRYP_STATE_BUSY;
1303
1304 /* Process locked */
1305 __HAL_LOCK(hcryp);
1306
1307 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1308 hcryp->CrypInCount = 0U;
1309 hcryp->CrypOutCount = 0U;
1310 hcryp->pCrypInBuffPtr = Input;
1311 hcryp->pCrypOutBuffPtr = Output;
1312
1313 /* Calculate Size parameter in Byte*/
1314 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1315 {
1316 hcryp->Size = Size * 4U;
1317 }
1318 else
1319 {
1320 hcryp->Size = Size;
1321 }
1322
1323#if defined (CRYP)
1324
1325 /* Set encryption operating mode*/
1326 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1327
1328 /* algo get algorithm selected */
1329 algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
1330
1331 switch (algo)
1332 {
1333 case CRYP_DES_ECB:
1334 case CRYP_DES_CBC:
1335 case CRYP_TDES_ECB:
1336 case CRYP_TDES_CBC:
1337
1338 /*Set Key */
1339 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1340 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1341 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1342 {
1343 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1344 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1345 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1346 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1347 }
1348 /* Set the Initialization Vector*/
1349 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1350 {
1351 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1352 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1353 }
1354
1355 /* Flush FIFO */
1356 HAL_CRYP_FIFO_FLUSH(hcryp);
1357
1358 /* Set the phase */
1359 hcryp->Phase = CRYP_PHASE_PROCESS;
1360
1361 /* Enable interrupts */
1362 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1363
1364 /* Enable CRYP to start DES/TDES process*/
1365 __HAL_CRYP_ENABLE(hcryp);
1366 break;
1367
1368 case CRYP_AES_ECB:
1369 case CRYP_AES_CBC:
1370 case CRYP_AES_CTR:
1371
1372 status = CRYP_AES_Encrypt_IT(hcryp);
1373 break;
1374#if defined (CRYP_CR_ALGOMODE_AES_GCM)
1375 case CRYP_AES_GCM:
1376
1377 status = CRYP_AESGCM_Process_IT(hcryp) ;
1378 break;
1379
1380 case CRYP_AES_CCM:
1381
1382 status = CRYP_AESCCM_Process_IT(hcryp);
1383 break;
1384#endif /* GCM CCM defined*/
1385 default:
1386 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1387 /* Change the CRYP peripheral state */
1388 hcryp->State = HAL_CRYP_STATE_READY;
1389 /* Process unlocked */
1390 __HAL_UNLOCK(hcryp);
1391 status = HAL_ERROR;
1392 break;
1393 }
1394
1395#else /* AES */
1396
1397 /* Set encryption operating mode*/
1398 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1399
1400 /* algo get algorithm selected */
1401 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1402
1403 switch (algo)
1404 {
1405 case CRYP_AES_ECB:
1406 case CRYP_AES_CBC:
1407 case CRYP_AES_CTR:
1408
1409 /* AES encryption */
1410 status = CRYP_AES_Encrypt_IT(hcryp);
1411 break;
1412
1413 case CRYP_AES_GCM_GMAC:
1414
1415 /* AES GCM encryption */
1416 status = CRYP_AESGCM_Process_IT(hcryp) ;
1417 break;
1418
1419 case CRYP_AES_CCM:
1420
1421 /* AES CCM encryption */
1422 status = CRYP_AESCCM_Process_IT(hcryp);
1423 break;
1424
1425 default:
1426 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1427 /* Change the CRYP peripheral state */
1428 hcryp->State = HAL_CRYP_STATE_READY;
1429 /* Process unlocked */
1430 __HAL_UNLOCK(hcryp);
1431 status = HAL_ERROR;
1432 break;
1433 }
1434#endif /*end AES or CRYP*/
1435
1436 }
1437 else
1438 {
1439 /* Busy error code field */
1440 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1441 status = HAL_ERROR;
1442 }
1443
1444 /* Return function status */
1445 return status;
1446}
1447
1457HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1458{
1459 uint32_t algo;
1460 HAL_StatusTypeDef status = HAL_OK;
1461
1462 if (hcryp->State == HAL_CRYP_STATE_READY)
1463 {
1464 /* Change state Busy */
1465 hcryp->State = HAL_CRYP_STATE_BUSY;
1466
1467 /* Process locked */
1468 __HAL_LOCK(hcryp);
1469
1470 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1471 hcryp->CrypInCount = 0U;
1472 hcryp->CrypOutCount = 0U;
1473 hcryp->pCrypInBuffPtr = Input;
1474 hcryp->pCrypOutBuffPtr = Output;
1475
1476 /* Calculate Size parameter in Byte*/
1477 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1478 {
1479 hcryp->Size = Size * 4U;
1480 }
1481 else
1482 {
1483 hcryp->Size = Size;
1484 }
1485
1486#if defined (CRYP)
1487
1488 /* Set decryption operating mode*/
1489 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1490
1491 /* algo get algorithm selected */
1492 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1493
1494 switch (algo)
1495 {
1496 case CRYP_DES_ECB:
1497 case CRYP_DES_CBC:
1498 case CRYP_TDES_ECB:
1499 case CRYP_TDES_CBC:
1500
1501 /*Set Key */
1502 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1503 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1504 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1505 {
1506 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1507 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1508 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1509 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1510 }
1511
1512 /* Set the Initialization Vector*/
1513 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1514 {
1515 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1516 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1517 }
1518 /* Flush FIFO */
1519 HAL_CRYP_FIFO_FLUSH(hcryp);
1520
1521 /* Set the phase */
1522 hcryp->Phase = CRYP_PHASE_PROCESS;
1523
1524 /* Enable interrupts */
1525 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1526
1527 /* Enable CRYP and start DES/TDES process*/
1528 __HAL_CRYP_ENABLE(hcryp);
1529
1530 break;
1531
1532 case CRYP_AES_ECB:
1533 case CRYP_AES_CBC:
1534 case CRYP_AES_CTR:
1535
1536 /* AES decryption */
1537 status = CRYP_AES_Decrypt_IT(hcryp);
1538 break;
1539#if defined (CRYP_CR_ALGOMODE_AES_GCM)
1540 case CRYP_AES_GCM:
1541
1542 /* AES GCM decryption */
1543 status = CRYP_AESGCM_Process_IT(hcryp) ;
1544 break;
1545
1546 case CRYP_AES_CCM:
1547
1548 /* AES CCMdecryption */
1549 status = CRYP_AESCCM_Process_IT(hcryp);
1550 break;
1551#endif /* GCM CCM defined*/
1552 default:
1553 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1554 /* Change the CRYP peripheral state */
1555 hcryp->State = HAL_CRYP_STATE_READY;
1556 /* Process unlocked */
1557 __HAL_UNLOCK(hcryp);
1558 status = HAL_ERROR;
1559 break;
1560 }
1561
1562#else /*AES*/
1563
1564 /* Set decryption operating mode*/
1565 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1566
1567 /* algo get algorithm selected */
1568 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1569
1570 switch (algo)
1571 {
1572 case CRYP_AES_ECB:
1573 case CRYP_AES_CBC:
1574 case CRYP_AES_CTR:
1575
1576 /* AES decryption */
1577 status = CRYP_AES_Decrypt_IT(hcryp);
1578 break;
1579
1580 case CRYP_AES_GCM_GMAC:
1581
1582 /* AES GCM decryption */
1583 status = CRYP_AESGCM_Process_IT(hcryp) ;
1584 break;
1585
1586 case CRYP_AES_CCM:
1587
1588 /* AES CCM decryption */
1589 status = CRYP_AESCCM_Process_IT(hcryp);
1590 break;
1591
1592 default:
1593 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1594 /* Change the CRYP peripheral state */
1595 hcryp->State = HAL_CRYP_STATE_READY;
1596 /* Process unlocked */
1597 __HAL_UNLOCK(hcryp);
1598 status = HAL_ERROR;
1599 break;
1600 }
1601#endif /* End AES or CRYP */
1602
1603 }
1604 else
1605 {
1606 /* Busy error code field */
1607 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1608 status = HAL_ERROR;
1609 }
1610
1611 /* Return function status */
1612 return status;
1613}
1614
1624HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1625{
1626 uint32_t algo;
1627 HAL_StatusTypeDef status = HAL_OK;
1628 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
1629
1630 if (hcryp->State == HAL_CRYP_STATE_READY)
1631 {
1632 /* Change state Busy */
1633 hcryp->State = HAL_CRYP_STATE_BUSY;
1634
1635 /* Process locked */
1636 __HAL_LOCK(hcryp);
1637
1638 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1639 hcryp->CrypInCount = 0U;
1640 hcryp->CrypOutCount = 0U;
1641 hcryp->pCrypInBuffPtr = Input;
1642 hcryp->pCrypOutBuffPtr = Output;
1643
1644 /* Calculate Size parameter in Byte*/
1645 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1646 {
1647 hcryp->Size = Size * 4U;
1648 }
1649 else
1650 {
1651 hcryp->Size = Size;
1652 }
1653
1654#if defined (CRYP)
1655
1656 /* Set encryption operating mode*/
1657 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1658
1659 /* algo get algorithm selected */
1660 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1661
1662 switch (algo)
1663 {
1664 case CRYP_DES_ECB:
1665 case CRYP_DES_CBC:
1666 case CRYP_TDES_ECB:
1667 case CRYP_TDES_CBC:
1668
1669 /*Set Key */
1670 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1671 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1672 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1673 {
1674 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1675 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1676 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1677 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1678 }
1679
1680 /* Set the Initialization Vector*/
1681 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1682 {
1683 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1684 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1685 }
1686
1687 /* Flush FIFO */
1688 HAL_CRYP_FIFO_FLUSH(hcryp);
1689
1690 /* Set the phase */
1691 hcryp->Phase = CRYP_PHASE_PROCESS;
1692
1693 /* Start DMA process transfer for DES/TDES */
1694 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1695 (uint32_t)(hcryp->pCrypOutBuffPtr));
1696 break;
1697
1698 case CRYP_AES_ECB:
1699 case CRYP_AES_CBC:
1700 case CRYP_AES_CTR:
1701
1702 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
1703 {
1704 if (hcryp->KeyIVConfig == 1U)
1705 {
1706 /* If the Key and IV configuration has to be done only once
1707 and if it has already been done, skip it */
1708 DoKeyIVConfig = 0U;
1709 }
1710 else
1711 {
1712 /* If the Key and IV configuration has to be done only once
1713 and if it has not been done already, do it and set KeyIVConfig
1714 to keep track it won't have to be done again next time */
1715 hcryp->KeyIVConfig = 1U;
1716 }
1717 }
1718
1719 if (DoKeyIVConfig == 1U)
1720 {
1721 /* Set the Key*/
1722 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1723
1724 /* Set the Initialization Vector*/
1725 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1726 {
1727 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1728 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
1729 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
1730 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
1731 }
1732 } /* if (DoKeyIVConfig == 1U) */
1733
1734 /* Set the phase */
1735 hcryp->Phase = CRYP_PHASE_PROCESS;
1736
1737 /* Start DMA process transfer for AES */
1738 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1739 (uint32_t)(hcryp->pCrypOutBuffPtr));
1740 break;
1741#if defined (CRYP_CR_ALGOMODE_AES_GCM)
1742 case CRYP_AES_GCM:
1743 /* AES GCM encryption */
1744 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1745 break;
1746
1747 case CRYP_AES_CCM:
1748 /* AES CCM encryption */
1749 status = CRYP_AESCCM_Process_DMA(hcryp);
1750 break;
1751#endif /* GCM CCM defined*/
1752 default:
1753 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1754 /* Change the CRYP peripheral state */
1755 hcryp->State = HAL_CRYP_STATE_READY;
1756 /* Process unlocked */
1757 __HAL_UNLOCK(hcryp);
1758 status = HAL_ERROR;
1759 break;
1760 }
1761
1762#else /*AES*/
1763 /* Set encryption operating mode*/
1764 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1765
1766 /* algo get algorithm selected */
1767 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1768
1769 switch (algo)
1770 {
1771
1772 case CRYP_AES_ECB:
1773 case CRYP_AES_CBC:
1774 case CRYP_AES_CTR:
1775
1776 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
1777 {
1778 if (hcryp->KeyIVConfig == 1U)
1779 {
1780 /* If the Key and IV configuration has to be done only once
1781 and if it has already been done, skip it */
1782 DoKeyIVConfig = 0U;
1783 }
1784 else
1785 {
1786 /* If the Key and IV configuration has to be done only once
1787 and if it has not been done already, do it and set KeyIVConfig
1788 to keep track it won't have to be done again next time */
1789 hcryp->KeyIVConfig = 1U;
1790 }
1791 }
1792
1793 if (DoKeyIVConfig == 1U)
1794 {
1795 /* Set the Key*/
1796 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1797
1798 /* Set the Initialization Vector*/
1799 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1800 {
1801 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
1802 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1803 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
1804 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
1805 }
1806 } /* if (DoKeyIVConfig == 1U) */
1807 /* Set the phase */
1808 hcryp->Phase = CRYP_PHASE_PROCESS;
1809
1810 /* Start DMA process transfer for AES */
1811 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr),
1812 (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
1813 break;
1814
1815 case CRYP_AES_GCM_GMAC:
1816 /* AES GCM encryption */
1817 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1818 break;
1819
1820 case CRYP_AES_CCM:
1821 /* AES CCM encryption */
1822 status = CRYP_AESCCM_Process_DMA(hcryp);
1823 break;
1824
1825 default:
1826 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1827 /* Change the CRYP peripheral state */
1828 hcryp->State = HAL_CRYP_STATE_READY;
1829 /* Process unlocked */
1830 __HAL_UNLOCK(hcryp);
1831 status = HAL_ERROR;
1832 break;
1833 }
1834#endif /* End AES or CRYP */
1835
1836 }
1837 else
1838 {
1839 /* Busy error code field */
1840 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1841 status = HAL_ERROR;
1842 }
1843
1844 /* Return function status */
1845 return status;
1846}
1847
1857HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1858{
1859 uint32_t algo;
1860 HAL_StatusTypeDef status = HAL_OK;
1861
1862 if (hcryp->State == HAL_CRYP_STATE_READY)
1863 {
1864
1865 /* Change state Busy */
1866 hcryp->State = HAL_CRYP_STATE_BUSY;
1867
1868 /* Process locked */
1869 __HAL_LOCK(hcryp);
1870
1871 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1872 hcryp->CrypInCount = 0U;
1873 hcryp->CrypOutCount = 0U;
1874 hcryp->pCrypInBuffPtr = Input;
1875 hcryp->pCrypOutBuffPtr = Output;
1876
1877 /* Calculate Size parameter in Byte*/
1878 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1879 {
1880 hcryp->Size = Size * 4U;
1881 }
1882 else
1883 {
1884 hcryp->Size = Size;
1885 }
1886
1887#if defined (CRYP)
1888
1889 /* Set decryption operating mode*/
1890 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1891
1892 /* algo get algorithm selected */
1893 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1894
1895 switch (algo)
1896 {
1897 case CRYP_DES_ECB:
1898 case CRYP_DES_CBC:
1899 case CRYP_TDES_ECB:
1900 case CRYP_TDES_CBC:
1901
1902 /*Set Key */
1903 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1904 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1905 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1906 {
1907 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1908 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1909 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1910 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1911 }
1912
1913 /* Set the Initialization Vector*/
1914 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1915 {
1916 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1917 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1918 }
1919
1920 /* Flush FIFO */
1921 HAL_CRYP_FIFO_FLUSH(hcryp);
1922
1923 /* Set the phase */
1924 hcryp->Phase = CRYP_PHASE_PROCESS;
1925
1926 /* Start DMA process transfer for DES/TDES */
1927 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1928 (uint32_t)(hcryp->pCrypOutBuffPtr));
1929 break;
1930
1931 case CRYP_AES_ECB:
1932 case CRYP_AES_CBC:
1933 case CRYP_AES_CTR:
1934
1935 /* AES decryption */
1936 status = CRYP_AES_Decrypt_DMA(hcryp);
1937 break;
1938#if defined (CRYP_CR_ALGOMODE_AES_GCM)
1939 case CRYP_AES_GCM:
1940 /* AES GCM decryption */
1941 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1942 break;
1943
1944 case CRYP_AES_CCM:
1945 /* AES CCM decryption */
1946 status = CRYP_AESCCM_Process_DMA(hcryp);
1947 break;
1948#endif /* GCM CCM defined*/
1949 default:
1950 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1951 /* Change the CRYP peripheral state */
1952 hcryp->State = HAL_CRYP_STATE_READY;
1953 /* Process unlocked */
1954 __HAL_UNLOCK(hcryp);
1955 status = HAL_ERROR;
1956 break;
1957 }
1958
1959#else /*AES*/
1960
1961 /* Set decryption operating mode*/
1962 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1963
1964 /* algo get algorithm selected */
1965 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1966
1967 switch (algo)
1968 {
1969
1970 case CRYP_AES_ECB:
1971 case CRYP_AES_CBC:
1972 case CRYP_AES_CTR:
1973
1974 /* AES decryption */
1975 status = CRYP_AES_Decrypt_DMA(hcryp);
1976 break;
1977
1978 case CRYP_AES_GCM_GMAC:
1979 /* AES GCM decryption */
1980 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1981 break;
1982
1983 case CRYP_AES_CCM:
1984 /* AES CCM decryption */
1985 status = CRYP_AESCCM_Process_DMA(hcryp);
1986 break;
1987
1988 default:
1989 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1990 /* Change the CRYP peripheral state */
1991 hcryp->State = HAL_CRYP_STATE_READY;
1992 /* Process unlocked */
1993 __HAL_UNLOCK(hcryp);
1994 status = HAL_ERROR;
1995 break;
1996 }
1997#endif /* End AES or CRYP */
1998 }
1999 else
2000 {
2001 /* Busy error code field */
2002 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
2003 status = HAL_ERROR;
2004 }
2005
2006 /* Return function status */
2007 return status;
2008}
2009
2013
2031
2038void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
2039{
2040
2041#if defined (CRYP)
2042
2043 uint32_t itstatus = hcryp->Instance->MISR;
2044
2045 if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U)
2046 {
2047 if ((hcryp->Init.Algorithm == CRYP_DES_ECB) || (hcryp->Init.Algorithm == CRYP_DES_CBC)
2048 || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
2049 {
2050 CRYP_TDES_IT(hcryp); /* DES or TDES*/
2051 }
2052 else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC)
2053 || (hcryp->Init.Algorithm == CRYP_AES_CTR))
2054 {
2055 CRYP_AES_IT(hcryp); /*AES*/
2056 }
2057#if defined (CRYP_CR_ALGOMODE_AES_GCM)
2058 else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM))
2059 {
2060 /* if header phase */
2061 if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
2062 {
2063 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2064 }
2065 else /* if payload phase */
2066 {
2067 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2068 }
2069 }
2070#endif /* GCM CCM defined*/
2071 else
2072 {
2073 /* Nothing to do */
2074 }
2075 }
2076
2077#else /*AES*/
2078 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET)
2079 {
2080 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
2081 {
2082
2083 /* Clear computation complete flag */
2084 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2085
2086 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
2087 {
2088
2089 /* if header phase */
2090 if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
2091 {
2092 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2093 }
2094 else /* if payload phase */
2095 {
2096 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2097 }
2098 }
2099 else if (hcryp->Init.Algorithm == CRYP_AES_CCM)
2100 {
2101 /* if header phase */
2102 if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount)
2103 {
2104 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2105 }
2106 else /* if payload phase */
2107 {
2108 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2109 }
2110 }
2111 else /* AES Algorithm ECB,CBC or CTR*/
2112 {
2113 CRYP_AES_IT(hcryp);
2114 }
2115 }
2116 }
2117 /* Check if error occurred */
2118 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERRIE) != RESET)
2119 {
2120 /* If write Error occurred */
2121 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_WRERR) != RESET)
2122 {
2123 hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
2124 }
2125 /* If read Error occurred */
2126 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_RDERR) != RESET)
2127 {
2128 hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
2129 }
2130 }
2131#endif /* End AES or CRYP */
2132}
2133
2140uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
2141{
2142 return hcryp->ErrorCode;
2143}
2144
2151HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
2152{
2153 return hcryp->State;
2154}
2155
2162__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
2163{
2164 /* Prevent unused argument(s) compilation warning */
2165 UNUSED(hcryp);
2166
2167 /* NOTE : This function should not be modified, when the callback is needed,
2168 the HAL_CRYP_InCpltCallback can be implemented in the user file
2169 */
2170}
2171
2178__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
2179{
2180 /* Prevent unused argument(s) compilation warning */
2181 UNUSED(hcryp);
2182
2183 /* NOTE : This function should not be modified, when the callback is needed,
2184 the HAL_CRYP_OutCpltCallback can be implemented in the user file
2185 */
2186}
2187
2194__weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
2195{
2196 /* Prevent unused argument(s) compilation warning */
2197 UNUSED(hcryp);
2198
2199 /* NOTE : This function Should not be modified, when the callback is needed,
2200 the HAL_CRYP_ErrorCallback could be implemented in the user file
2201 */
2202}
2206
2207/* Private functions ---------------------------------------------------------*/
2211
2212#if defined (CRYP)
2213
2221static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2222{
2223 uint32_t temp[2]; /* Temporary CrypOutBuff */
2224 uint16_t incount; /* Temporary CrypInCount Value */
2225 uint16_t outcount; /* Temporary CrypOutCount Value */
2226 uint32_t i;
2227
2228 /* Enable CRYP */
2229 __HAL_CRYP_ENABLE(hcryp);
2230 /*Temporary CrypOutCount Value*/
2231 outcount = hcryp->CrypOutCount;
2232
2233 /*Start processing*/
2234 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2235 {
2236 /* Temporary CrypInCount Value */
2237 incount = hcryp->CrypInCount;
2238 /* Write plain data and get cipher data */
2239 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
2240 {
2241 /* Write the input block in the IN FIFO */
2242 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2243 hcryp->CrypInCount++;
2244 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2245 hcryp->CrypInCount++;
2246 }
2247
2248 /* Wait for OFNE flag to be raised */
2249 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
2250 {
2251 /* Disable the CRYP peripheral clock */
2252 __HAL_CRYP_DISABLE(hcryp);
2253
2254 /* Change state & errorCode*/
2255 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2256 hcryp->State = HAL_CRYP_STATE_READY;
2257
2258 /* Process unlocked */
2259 __HAL_UNLOCK(hcryp);
2260#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2261 /*Call registered error callback*/
2262 hcryp->ErrorCallback(hcryp);
2263#else
2264 /*Call legacy weak error callback*/
2265 HAL_CRYP_ErrorCallback(hcryp);
2266#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2267 }
2268
2269 /*Temporary CrypOutCount Value*/
2270 outcount = hcryp->CrypOutCount;
2271
2272 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
2273 {
2274 /* Read the output block from the Output FIFO and put them in temporary Buffer
2275 then get CrypOutBuff from temporary buffer */
2276 for (i = 0U; i < 2U; i++)
2277 {
2278 temp[i] = hcryp->Instance->DOUT;
2279 }
2280 i = 0U;
2281 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U))
2282 {
2283 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
2284 hcryp->CrypOutCount++;
2285 i++;
2286 }
2287 }
2288 /*Temporary CrypOutCount Value*/
2289 outcount = hcryp->CrypOutCount;
2290 }
2291 /* Disable CRYP */
2292 __HAL_CRYP_DISABLE(hcryp);
2293 /* Change the CRYP state */
2294 hcryp->State = HAL_CRYP_STATE_READY;
2295
2296 /* Return function status */
2297 return HAL_OK;
2298}
2299
2308static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
2309{
2310 uint32_t temp[2]; /* Temporary CrypOutBuff */
2311 uint32_t i;
2312
2313 if (hcryp->State == HAL_CRYP_STATE_BUSY)
2314 {
2315 if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U)
2316 {
2317 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U)
2318 {
2319 /* Write input block in the IN FIFO */
2320 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2321 hcryp->CrypInCount++;
2322 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2323 hcryp->CrypInCount++;
2324
2325 if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U))
2326 {
2327 /* Disable interruption */
2328 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
2329 /* Call the input data transfer complete callback */
2330#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
2331 /*Call registered Input complete callback*/
2332 hcryp->InCpltCallback(hcryp);
2333#else
2334 /*Call legacy weak Input complete callback*/
2335 HAL_CRYP_InCpltCallback(hcryp);
2336#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2337 }
2338 }
2339 }
2340 if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)
2341 {
2342 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U)
2343 {
2344 /* Read the output block from the Output FIFO and put them in temporary Buffer
2345 then get CrypOutBuff from temporary buffer */
2346 for (i = 0U; i < 2U; i++)
2347 {
2348 temp[i] = hcryp->Instance->DOUT;
2349 }
2350 i = 0U;
2351 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U))
2352 {
2353 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
2354 hcryp->CrypOutCount++;
2355 i++;
2356 }
2357 if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U))
2358 {
2359 /* Disable interruption */
2360 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
2361
2362 /* Disable CRYP */
2363 __HAL_CRYP_DISABLE(hcryp);
2364
2365 /* Process unlocked */
2366 __HAL_UNLOCK(hcryp);
2367
2368 /* Change the CRYP state */
2369 hcryp->State = HAL_CRYP_STATE_READY;
2370 /* Call output transfer complete callback */
2371#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2372 /*Call registered Output complete callback*/
2373 hcryp->OutCpltCallback(hcryp);
2374#else
2375 /*Call legacy weak Output complete callback*/
2376 HAL_CRYP_OutCpltCallback(hcryp);
2377#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2378 }
2379 }
2380 }
2381 }
2382 else
2383 {
2384 /* Process unlocked */
2385 __HAL_UNLOCK(hcryp);
2386 /* Busy error code field */
2387 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
2388#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2389 /*Call registered error callback*/
2390 hcryp->ErrorCallback(hcryp);
2391#else
2392 /*Call legacy weak error callback*/
2393 HAL_CRYP_ErrorCallback(hcryp);
2394#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2395 }
2396}
2397
2398#endif /* CRYP */
2399
2406static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2407{
2408 uint16_t outcount; /* Temporary CrypOutCount Value */
2409 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2410
2411 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2412 {
2413 if (hcryp->KeyIVConfig == 1U)
2414 {
2415 /* If the Key and IV configuration has to be done only once
2416 and if it has already been done, skip it */
2417 DoKeyIVConfig = 0U;
2418 }
2419 else
2420 {
2421 /* If the Key and IV configuration has to be done only once
2422 and if it has not been done already, do it and set KeyIVConfig
2423 to keep track it won't have to be done again next time */
2424 hcryp->KeyIVConfig = 1U;
2425 }
2426 }
2427
2428 if (DoKeyIVConfig == 1U)
2429 {
2430
2431 /* Set the Key*/
2432 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2433
2434 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2435 {
2436 /* Set the Initialization Vector*/
2437#if defined (AES)
2438 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2439 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2440 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2441 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2442#else /* CRYP */
2443 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2444 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2445 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2446 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2447#endif /* End AES or CRYP */
2448 }
2449 } /* if (DoKeyIVConfig == 1U) */
2450
2451 /* Set the phase */
2452 hcryp->Phase = CRYP_PHASE_PROCESS;
2453
2454 /* Enable CRYP */
2455 __HAL_CRYP_ENABLE(hcryp);
2456
2457 /*Temporary CrypOutCount Value*/
2458 outcount = hcryp->CrypOutCount;
2459
2460 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2461 {
2462 /* Write plain Ddta and get cipher data */
2463 CRYP_AES_ProcessData(hcryp, Timeout);
2464 /*Temporary CrypOutCount Value*/
2465 outcount = hcryp->CrypOutCount;
2466 }
2467
2468 /* Disable CRYP */
2469 __HAL_CRYP_DISABLE(hcryp);
2470
2471 /* Change the CRYP state */
2472 hcryp->State = HAL_CRYP_STATE_READY;
2473
2474 /* Return function status */
2475 return HAL_OK;
2476}
2477
2484static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
2485{
2486 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2487
2488 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2489 {
2490 if (hcryp->KeyIVConfig == 1U)
2491 {
2492 /* If the Key and IV configuration has to be done only once
2493 and if it has already been done, skip it */
2494 DoKeyIVConfig = 0U;
2495 }
2496 else
2497 {
2498 /* If the Key and IV configuration has to be done only once
2499 and if it has not been done already, do it and set KeyIVConfig
2500 to keep track it won't have to be done again next time */
2501 hcryp->KeyIVConfig = 1U;
2502 }
2503 }
2504
2505 if (DoKeyIVConfig == 1U)
2506 {
2507 /* Set the Key*/
2508 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2509
2510 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2511 {
2512 /* Set the Initialization Vector*/
2513#if defined (AES)
2514 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2515 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2516 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2517 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2518
2519#else /* CRYP */
2520 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2521 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2522 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2523 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2524#endif /* End AES or CRYP */
2525 }
2526 } /* if (DoKeyIVConfig == 1U) */
2527
2528 /* Set the phase */
2529 hcryp->Phase = CRYP_PHASE_PROCESS;
2530
2531 if (hcryp->Size != 0U)
2532 {
2533#if defined (AES)
2534
2535 /* Enable computation complete flag and error interrupts */
2536 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
2537
2538 /* Enable CRYP */
2539 __HAL_CRYP_ENABLE(hcryp);
2540
2541 /* Increment the pointer before writing the input block in the IN FIFO to make sure that
2542 when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value
2543 and it is ready for the next operation. */
2544 hcryp->CrypInCount++;
2545 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2546 hcryp->CrypInCount++;
2547 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2548 hcryp->CrypInCount++;
2549 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2550 hcryp->CrypInCount++;
2551 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2552
2553#else /* CRYP */
2554
2555 /* Enable interrupts */
2556 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2557
2558 /* Enable CRYP */
2559 __HAL_CRYP_ENABLE(hcryp);
2560
2561#endif /* End AES or CRYP */
2562 }
2563 else
2564 {
2565 /* Change the CRYP state */
2566 hcryp->State = HAL_CRYP_STATE_READY;
2567
2568 /* Process unlocked */
2569 __HAL_UNLOCK(hcryp);
2570 }
2571
2572 /* Return function status */
2573 return HAL_OK;
2574}
2575
2582static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2583{
2584 uint16_t outcount; /* Temporary CrypOutCount Value */
2585 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2586
2587 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2588 {
2589 if (hcryp->KeyIVConfig == 1U)
2590 {
2591 /* If the Key and IV configuration has to be done only once
2592 and if it has already been done, skip it */
2593 DoKeyIVConfig = 0U;
2594 }
2595 else
2596 {
2597 /* If the Key and IV configuration has to be done only once
2598 and if it has not been done already, do it and set KeyIVConfig
2599 to keep track it won't have to be done again next time */
2600 hcryp->KeyIVConfig = 1U;
2601 }
2602 }
2603
2604 if (DoKeyIVConfig == 1U)
2605 {
2606 /* Key preparation for ECB/CBC */
2607 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2608 {
2609#if defined (AES)
2610 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
2611 {
2612 /* Set key preparation for decryption operating mode*/
2613 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2614
2615 /* Set the Key*/
2616 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2617
2618 /* Enable CRYP */
2619 __HAL_CRYP_ENABLE(hcryp);
2620
2621 /* Wait for CCF flag to be raised */
2622 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
2623 {
2624 /* Disable the CRYP peripheral clock */
2625 __HAL_CRYP_DISABLE(hcryp);
2626
2627 /* Change state & error code*/
2628 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2629 hcryp->State = HAL_CRYP_STATE_READY;
2630
2631 /* Process unlocked */
2632 __HAL_UNLOCK(hcryp);
2633 return HAL_ERROR;
2634 }
2635 /* Clear CCF Flag */
2636 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2637
2638 /* Return to decryption operating mode(Mode 3)*/
2639 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2640 }
2641 else /*Mode 4 : decryption & Key preparation*/
2642 {
2643 /* Set the Key*/
2644 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2645
2646 /* Set decryption & Key preparation operating mode*/
2647 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2648 }
2649#else /* CRYP */
2650 /* change ALGOMODE to key preparation for decryption*/
2651 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2652
2653 /* Set the Key*/
2654 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2655
2656 /* Enable CRYP */
2657 __HAL_CRYP_ENABLE(hcryp);
2658
2659 /* Wait for BUSY flag to be raised */
2660 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
2661 {
2662 /* Disable the CRYP peripheral clock */
2663 __HAL_CRYP_DISABLE(hcryp);
2664
2665 /* Change state */
2666 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2667 hcryp->State = HAL_CRYP_STATE_READY;
2668
2669 /* Process unlocked */
2670 __HAL_UNLOCK(hcryp);
2671 return HAL_ERROR;
2672 }
2673 /* Turn back to ALGOMODE of the configuration */
2674 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2675
2676#endif /* End AES or CRYP */
2677 }
2678 else /*Algorithm CTR */
2679 {
2680 /* Set the Key*/
2681 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2682 }
2683
2684 /* Set IV */
2685 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2686 {
2687 /* Set the Initialization Vector*/
2688#if defined (AES)
2689 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2690 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2691 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2692 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2693#else /* CRYP */
2694 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2695 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2696 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2697 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2698#endif /* End AES or CRYP */
2699 }
2700 } /* if (DoKeyIVConfig == 1U) */
2701 /* Set the phase */
2702 hcryp->Phase = CRYP_PHASE_PROCESS;
2703
2704 /* Enable CRYP */
2705 __HAL_CRYP_ENABLE(hcryp);
2706
2707 /*Temporary CrypOutCount Value*/
2708 outcount = hcryp->CrypOutCount;
2709
2710 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2711 {
2712 /* Write plain data and get cipher data */
2713 CRYP_AES_ProcessData(hcryp, Timeout);
2714 /*Temporary CrypOutCount Value*/
2715 outcount = hcryp->CrypOutCount;
2716 }
2717
2718 /* Disable CRYP */
2719 __HAL_CRYP_DISABLE(hcryp);
2720
2721 /* Change the CRYP state */
2722 hcryp->State = HAL_CRYP_STATE_READY;
2723
2724 /* Return function status */
2725 return HAL_OK;
2726}
2733static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
2734{
2735 __IO uint32_t count = 0U;
2736 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2737
2738 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2739 {
2740 if (hcryp->KeyIVConfig == 1U)
2741 {
2742 /* If the Key and IV configuration has to be done only once
2743 and if it has already been done, skip it */
2744 DoKeyIVConfig = 0U;
2745 }
2746 else
2747 {
2748 /* If the Key and IV configuration has to be done only once
2749 and if it has not been done already, do it and set KeyIVConfig
2750 to keep track it won't have to be done again next time */
2751 hcryp->KeyIVConfig = 1U;
2752 }
2753 }
2754
2755 if (DoKeyIVConfig == 1U)
2756 {
2757 /* Key preparation for ECB/CBC */
2758 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2759 {
2760#if defined (AES)
2761 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
2762 {
2763 /* Set key preparation for decryption operating mode*/
2764 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2765
2766 /* Set the Key*/
2767 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2768
2769 /* Enable CRYP */
2770 __HAL_CRYP_ENABLE(hcryp);
2771
2772 /* Wait for CCF flag to be raised */
2773 count = CRYP_TIMEOUT_KEYPREPARATION;
2774 do
2775 {
2776 count-- ;
2777 if (count == 0U)
2778 {
2779 /* Disable the CRYP peripheral clock */
2780 __HAL_CRYP_DISABLE(hcryp);
2781
2782 /* Change state */
2783 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2784 hcryp->State = HAL_CRYP_STATE_READY;
2785
2786 /* Process unlocked */
2787 __HAL_UNLOCK(hcryp);
2788 return HAL_ERROR;
2789 }
2790 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
2791
2792 /* Clear CCF Flag */
2793 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2794
2795 /* Return to decryption operating mode(Mode 3)*/
2796 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2797 }
2798 else /*Mode 4 : decryption & key preparation*/
2799 {
2800 /* Set the Key*/
2801 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2802
2803 /* Set decryption & key preparation operating mode*/
2804 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2805 }
2806#else /* CRYP */
2807
2808 /* change ALGOMODE to key preparation for decryption*/
2809 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2810
2811 /* Set the Key*/
2812 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2813
2814 /* Enable CRYP */
2815 __HAL_CRYP_ENABLE(hcryp);
2816
2817 /* Wait for BUSY flag to be raised */
2818 count = CRYP_TIMEOUT_KEYPREPARATION;
2819 do
2820 {
2821 count-- ;
2822 if (count == 0U)
2823 {
2824 /* Change state */
2825 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2826 hcryp->State = HAL_CRYP_STATE_READY;
2827
2828 /* Process unlocked */
2829 __HAL_UNLOCK(hcryp);
2830 return HAL_ERROR;
2831 }
2832 } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
2833
2834 /* Turn back to ALGOMODE of the configuration */
2835 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2836
2837#endif /* End AES or CRYP */
2838 }
2839
2840 else /*Algorithm CTR */
2841 {
2842 /* Set the Key*/
2843 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2844 }
2845
2846 /* Set IV */
2847 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2848 {
2849 /* Set the Initialization Vector*/
2850#if defined (AES)
2851 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2852 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2853 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2854 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2855#else /* CRYP */
2856 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2857 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2858 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2859 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2860#endif /* End AES or CRYP */
2861 }
2862 } /* if (DoKeyIVConfig == 1U) */
2863
2864 /* Set the phase */
2865 hcryp->Phase = CRYP_PHASE_PROCESS;
2866 if (hcryp->Size != 0U)
2867 {
2868
2869#if defined (AES)
2870
2871 /* Enable computation complete flag and error interrupts */
2872 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
2873
2874 /* Enable CRYP */
2875 __HAL_CRYP_ENABLE(hcryp);
2876
2877 /* Increment the pointer before writing the input block in the IN FIFO to make sure that
2878 when Computation Completed IRQ fires, the hcryp->CrypInCount has always a consistent value
2879 and it is ready for the next operation. */
2880 hcryp->CrypInCount++;
2881 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2882 hcryp->CrypInCount++;
2883 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2884 hcryp->CrypInCount++;
2885 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2886 hcryp->CrypInCount++;
2887 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + (hcryp->CrypInCount - 1U));
2888
2889#else /* CRYP */
2890
2891 /* Enable interrupts */
2892 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2893
2894 /* Enable CRYP */
2895 __HAL_CRYP_ENABLE(hcryp);
2896
2897#endif /* End AES or CRYP */
2898 }
2899 else
2900 {
2901 /* Process locked */
2902 __HAL_UNLOCK(hcryp);
2903
2904 /* Change the CRYP state */
2905 hcryp->State = HAL_CRYP_STATE_READY;
2906 }
2907
2908 /* Return function status */
2909 return HAL_OK;
2910}
2917static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
2918{
2919 __IO uint32_t count = 0U;
2920 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2921
2922 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2923 {
2924 if (hcryp->KeyIVConfig == 1U)
2925 {
2926 /* If the Key and IV configuration has to be done only once
2927 and if it has already been done, skip it */
2928 DoKeyIVConfig = 0U;
2929 }
2930 else
2931 {
2932 /* If the Key and IV configuration has to be done only once
2933 and if it has not been done already, do it and set KeyIVConfig
2934 to keep track it won't have to be done again next time */
2935 hcryp->KeyIVConfig = 1U;
2936 }
2937 }
2938 if (DoKeyIVConfig == 1U)
2939 {
2940 /* Key preparation for ECB/CBC */
2941 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2942 {
2943#if defined (AES)
2944 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/
2945 {
2946 /* Set key preparation for decryption operating mode*/
2947 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2948
2949 /* Set the Key*/
2950 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2951
2952 /* Enable CRYP */
2953 __HAL_CRYP_ENABLE(hcryp);
2954
2955 /* Wait for CCF flag to be raised */
2956 count = CRYP_TIMEOUT_KEYPREPARATION;
2957 do
2958 {
2959 count-- ;
2960 if (count == 0U)
2961 {
2962 /* Disable the CRYP peripheral clock */
2963 __HAL_CRYP_DISABLE(hcryp);
2964
2965 /* Change state */
2966 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2967 hcryp->State = HAL_CRYP_STATE_READY;
2968
2969 /* Process unlocked */
2970 __HAL_UNLOCK(hcryp);
2971 return HAL_ERROR;
2972 }
2973 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
2974
2975 /* Clear CCF Flag */
2976 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2977
2978 /* Return to decryption operating mode(Mode 3)*/
2979 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2980 }
2981 else /*Mode 4 : decryption & key preparation*/
2982 {
2983 /* Set the Key*/
2984 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2985
2986 /* Set decryption & Key preparation operating mode*/
2987 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2988 }
2989#else /* CRYP */
2990 /* change ALGOMODE to key preparation for decryption*/
2991 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2992
2993 /* Set the Key*/
2994 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2995
2996 /* Enable CRYP */
2997 __HAL_CRYP_ENABLE(hcryp);
2998
2999 /* Wait for BUSY flag to be raised */
3000 count = CRYP_TIMEOUT_KEYPREPARATION;
3001 do
3002 {
3003 count-- ;
3004 if (count == 0U)
3005 {
3006 /* Disable the CRYP peripheral clock */
3007 __HAL_CRYP_DISABLE(hcryp);
3008
3009 /* Change state */
3010 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3011 hcryp->State = HAL_CRYP_STATE_READY;
3012
3013 /* Process unlocked */
3014 __HAL_UNLOCK(hcryp);
3015 return HAL_ERROR;
3016 }
3017 } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
3018
3019 /* Turn back to ALGOMODE of the configuration */
3020 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
3021
3022#endif /* End AES or CRYP */
3023 }
3024 else /*Algorithm CTR */
3025 {
3026 /* Set the Key*/
3027 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3028 }
3029
3030 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
3031 {
3032 /* Set the Initialization Vector*/
3033#if defined (AES)
3034 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3035 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3036 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3037 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3038#else /* CRYP */
3039 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3040 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3041 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3042 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3043#endif /* End AES or CRYP */
3044 }
3045 } /* if (DoKeyIVConfig == 1U) */
3046
3047 /* Set the phase */
3048 hcryp->Phase = CRYP_PHASE_PROCESS;
3049
3050 if (hcryp->Size != 0U)
3051 {
3052 /* Set the input and output addresses and start DMA transfer */
3053 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
3054 }
3055 else
3056 {
3057 /* Process unlocked */
3058 __HAL_UNLOCK(hcryp);
3059
3060 /* Change the CRYP state */
3061 hcryp->State = HAL_CRYP_STATE_READY;
3062 }
3063
3064 /* Return function status */
3065 return HAL_OK;
3066}
3067
3068
3074static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
3075{
3076 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3077
3078 /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
3079 in the DMACR register */
3080#if defined (CRYP)
3081 hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
3082
3083#else /* AES */
3084 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
3085
3086 /* TinyAES2, No output on CCM AES, unlock should be done when input data process complete */
3087 if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
3088 {
3089 /* Clear CCF flag */
3090 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3091
3092 /* Change the CRYP state to ready */
3093 hcryp->State = HAL_CRYP_STATE_READY;
3094
3095 /* Process Unlocked */
3096 __HAL_UNLOCK(hcryp);
3097 }
3098#endif /* End AES or CRYP */
3099
3100 /* Call input data transfer complete callback */
3101#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3102 /*Call registered Input complete callback*/
3103 hcryp->InCpltCallback(hcryp);
3104#else
3105 /*Call legacy weak Input complete callback*/
3106 HAL_CRYP_InCpltCallback(hcryp);
3107#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3108}
3109
3115static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
3116{
3117 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3118
3119 /* Disable the DMA transfer for output FIFO request by resetting
3120 the DOEN bit in the DMACR register */
3121
3122#if defined (CRYP)
3123
3124 hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
3125#if defined (CRYP_CR_ALGOMODE_AES_GCM)
3126 if ((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
3127 {
3128 /* Disable CRYP (not allowed in GCM)*/
3129 __HAL_CRYP_DISABLE(hcryp);
3130 }
3131
3132#else /*NO GCM CCM */
3133 /* Disable CRYP */
3134 __HAL_CRYP_DISABLE(hcryp);
3135#endif /* GCM CCM defined*/
3136#else /* AES */
3137
3138 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
3139
3140 /* Clear CCF flag */
3141 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3142
3143 if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
3144 {
3145 /* Disable CRYP (not allowed in GCM)*/
3146 __HAL_CRYP_DISABLE(hcryp);
3147 }
3148#endif /* End AES or CRYP */
3149
3150 /* Change the CRYP state to ready */
3151 hcryp->State = HAL_CRYP_STATE_READY;
3152
3153 /* Process unlocked */
3154 __HAL_UNLOCK(hcryp);
3155 /* Call output data transfer complete callback */
3156#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3157 /*Call registered Output complete callback*/
3158 hcryp->OutCpltCallback(hcryp);
3159#else
3160 /*Call legacy weak Output complete callback*/
3161 HAL_CRYP_OutCpltCallback(hcryp);
3162#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3163}
3164
3170static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
3171{
3172 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3173
3174 /* Change the CRYP peripheral state */
3175 hcryp->State = HAL_CRYP_STATE_READY;
3176
3177 /* DMA error code field */
3178 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3179
3180#if defined (AES)
3181
3182 /* Clear CCF flag */
3183 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3184
3185#endif /* AES */
3186
3187 /* Call error callback */
3188#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3189 /*Call registered error callback*/
3190 hcryp->ErrorCallback(hcryp);
3191#else
3192 /*Call legacy weak error callback*/
3193 HAL_CRYP_ErrorCallback(hcryp);
3194#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3195}
3196
3206static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
3207{
3208 /* Set the CRYP DMA transfer complete callback */
3209 hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
3210
3211 /* Set the DMA input error callback */
3212 hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
3213
3214 /* Set the CRYP DMA transfer complete callback */
3215 hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
3216
3217 /* Set the DMA output error callback */
3218 hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
3219
3220#if defined (CRYP)
3221
3222 /* Enable CRYP */
3223 __HAL_CRYP_ENABLE(hcryp);
3224
3225 /* Enable the input DMA Stream */
3226 if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size) != HAL_OK)
3227 {
3228 /* DMA error code field */
3229 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3230
3231 /* Call error callback */
3232#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3233 /*Call registered error callback*/
3234 hcryp->ErrorCallback(hcryp);
3235#else
3236 /*Call legacy weak error callback*/
3237 HAL_CRYP_ErrorCallback(hcryp);
3238#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3239 }
3240 /* Enable the output DMA Stream */
3241 if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size) != HAL_OK)
3242 {
3243 /* DMA error code field */
3244 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3245
3246 /* Call error callback */
3247#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3248 /*Call registered error callback*/
3249 hcryp->ErrorCallback(hcryp);
3250#else
3251 /*Call legacy weak error callback*/
3252 HAL_CRYP_ErrorCallback(hcryp);
3253#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3254 }
3255 /* Enable In/Out DMA request */
3256 hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN;
3257
3258#else /* AES */
3259
3260 if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
3261 && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
3262 {
3263 /* Enable CRYP (not allowed in GCM & CCM)*/
3264 __HAL_CRYP_ENABLE(hcryp);
3265 }
3266
3267 /* Enable the DMA input stream */
3268 if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
3269 {
3270 /* DMA error code field */
3271 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3272
3273 /* Call error callback */
3274#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3275 /*Call registered error callback*/
3276 hcryp->ErrorCallback(hcryp);
3277#else
3278 /*Call legacy weak error callback*/
3279 HAL_CRYP_ErrorCallback(hcryp);
3280#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3281 }
3282 /* Enable the DMA output stream */
3283 if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size) != HAL_OK)
3284 {
3285 /* DMA error code field */
3286 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3287
3288 /* Call error callback */
3289#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3290 /*Call registered error callback*/
3291 hcryp->ErrorCallback(hcryp);
3292#else
3293 /*Call legacy weak error callback*/
3294 HAL_CRYP_ErrorCallback(hcryp);
3295#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3296 }
3297 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
3298 /* Enable In and Out DMA requests */
3299 if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
3300 {
3301 /* Enable only In DMA requests for CCM*/
3302 SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN));
3303 }
3304 else
3305 {
3306 /* Enable In and Out DMA requests */
3307 SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
3308 }
3309#endif /* End AES or CRYP */
3310}
3311
3319static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3320{
3321
3322 uint32_t temp[4]; /* Temporary CrypOutBuff */
3323 uint32_t i;
3324#if defined (CRYP)
3325 uint16_t incount; /* Temporary CrypInCount Value */
3326 uint16_t outcount; /* Temporary CrypOutCount Value */
3327#endif /* CRYP */
3328
3329#if defined (CRYP)
3330
3331 /*Temporary CrypOutCount Value*/
3332 incount = hcryp->CrypInCount;
3333
3334 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
3335 {
3336 /* Write the input block in the IN FIFO */
3337 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3338 hcryp->CrypInCount++;
3339 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3340 hcryp->CrypInCount++;
3341 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3342 hcryp->CrypInCount++;
3343 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3344 hcryp->CrypInCount++;
3345 }
3346
3347 /* Wait for OFNE flag to be raised */
3348 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
3349 {
3350 /* Disable the CRYP peripheral clock */
3351 __HAL_CRYP_DISABLE(hcryp);
3352
3353 /* Change state & error code*/
3354 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3355 hcryp->State = HAL_CRYP_STATE_READY;
3356
3357 /* Process unlocked */
3358 __HAL_UNLOCK(hcryp);
3359#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3360 /*Call registered error callback*/
3361 hcryp->ErrorCallback(hcryp);
3362#else
3363 /*Call legacy weak error callback*/
3364 HAL_CRYP_ErrorCallback(hcryp);
3365#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3366 }
3367
3368 /*Temporary CrypOutCount Value*/
3369 outcount = hcryp->CrypOutCount;
3370
3371 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
3372 {
3373 /* Read the output block from the Output FIFO and put them in temporary buffer
3374 then get CrypOutBuff from temporary buffer */
3375 for (i = 0U; i < 4U; i++)
3376 {
3377 temp[i] = hcryp->Instance->DOUT;
3378 }
3379 i = 0U;
3380 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
3381 {
3382 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3383 hcryp->CrypOutCount++;
3384 i++;
3385 }
3386 }
3387
3388#else /* AES */
3389
3390 /* Write the input block in the IN FIFO */
3391 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3392 hcryp->CrypInCount++;
3393 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3394 hcryp->CrypInCount++;
3395 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3396 hcryp->CrypInCount++;
3397 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3398 hcryp->CrypInCount++;
3399
3400 /* Wait for CCF flag to be raised */
3401 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3402 {
3403 /* Disable the CRYP peripheral clock */
3404 __HAL_CRYP_DISABLE(hcryp);
3405
3406 /* Change state */
3407 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3408 hcryp->State = HAL_CRYP_STATE_READY;
3409
3410 /* Process unlocked */
3411 __HAL_UNLOCK(hcryp);
3412#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3413 /*Call registered error callback*/
3414 hcryp->ErrorCallback(hcryp);
3415#else
3416 /*Call legacy weak error callback*/
3417 HAL_CRYP_ErrorCallback(hcryp);
3418#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3419 }
3420
3421 /* Clear CCF Flag */
3422 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3423
3424 /* Read the output block from the output FIFO and put them in temporary buffer
3425 then get CrypOutBuff from temporary buffer*/
3426 for (i = 0U; i < 4U; i++)
3427 {
3428 temp[i] = hcryp->Instance->DOUTR;
3429 }
3430 i = 0U;
3431 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
3432 {
3433 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3434 hcryp->CrypOutCount++;
3435 i++;
3436 }
3437#endif /* End AES or CRYP */
3438}
3439
3448static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
3449{
3450 uint32_t temp[4]; /* Temporary CrypOutBuff */
3451 uint32_t i;
3452#if defined (CRYP)
3453 uint16_t incount; /* Temporary CrypInCount Value */
3454 uint16_t outcount; /* Temporary CrypOutCount Value */
3455#endif /* CRYP */
3456
3457 if (hcryp->State == HAL_CRYP_STATE_BUSY)
3458 {
3459#if defined (CRYP)
3460
3461 /*Temporary CrypOutCount Value*/
3462 incount = hcryp->CrypInCount;
3463 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
3464 {
3465 /* Write the input block in the IN FIFO */
3466 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3467 hcryp->CrypInCount++;
3468 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3469 hcryp->CrypInCount++;
3470 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3471 hcryp->CrypInCount++;
3472 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3473 hcryp->CrypInCount++;
3474 if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U))
3475 {
3476 /* Disable interrupts */
3477 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
3478
3479 /* Call the input data transfer complete callback */
3480#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3481 /*Call registered Input complete callback*/
3482 hcryp->InCpltCallback(hcryp);
3483#else
3484 /*Call legacy weak Input complete callback*/
3485 HAL_CRYP_InCpltCallback(hcryp);
3486#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3487 }
3488 }
3489 /*Temporary CrypOutCount Value*/
3490 outcount = hcryp->CrypOutCount;
3491
3492 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
3493 {
3494 /* Read the output block from the output FIFO and put them in temporary buffer
3495 then get CrypOutBuff from temporary buffer */
3496 for (i = 0U; i < 4U; i++)
3497 {
3498 temp[i] = hcryp->Instance->DOUT;
3499 }
3500 i = 0U;
3501 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
3502 {
3503 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3504 hcryp->CrypOutCount++;
3505 i++;
3506 }
3507 if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U))
3508 {
3509 /* Disable interrupts */
3510 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
3511
3512 /* Change the CRYP state */
3513 hcryp->State = HAL_CRYP_STATE_READY;
3514
3515 /* Disable CRYP */
3516 __HAL_CRYP_DISABLE(hcryp);
3517
3518 /* Process unlocked */
3519 __HAL_UNLOCK(hcryp);
3520
3521 /* Call Output transfer complete callback */
3522#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3523 /*Call registered Output complete callback*/
3524 hcryp->OutCpltCallback(hcryp);
3525#else
3526 /*Call legacy weak Output complete callback*/
3527 HAL_CRYP_OutCpltCallback(hcryp);
3528#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3529 }
3530 }
3531#else /*AES*/
3532
3533 /* Read the output block from the output FIFO and put them in temporary buffer
3534 then get CrypOutBuff from temporary buffer*/
3535 for (i = 0U; i < 4U; i++)
3536 {
3537 temp[i] = hcryp->Instance->DOUTR;
3538 }
3539 i = 0U;
3540 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
3541 {
3542 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3543 hcryp->CrypOutCount++;
3544 i++;
3545 }
3546
3547 if (hcryp->CrypOutCount == (hcryp->Size / 4U))
3548 {
3549 /* Disable Computation Complete flag and errors interrupts */
3550 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
3551
3552 /* Change the CRYP state */
3553 hcryp->State = HAL_CRYP_STATE_READY;
3554
3555 /* Disable CRYP */
3556 __HAL_CRYP_DISABLE(hcryp);
3557
3558 /* Process Unlocked */
3559 __HAL_UNLOCK(hcryp);
3560
3561 /* Call Output transfer complete callback */
3562#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3563 /*Call registered Output complete callback*/
3564 hcryp->OutCpltCallback(hcryp);
3565#else
3566 /*Call legacy weak Output complete callback*/
3567 HAL_CRYP_OutCpltCallback(hcryp);
3568#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3569 }
3570 else
3571 {
3572 /* Write the input block in the IN FIFO */
3573 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3574 hcryp->CrypInCount++;
3575 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3576 hcryp->CrypInCount++;
3577 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3578 hcryp->CrypInCount++;
3579 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3580 hcryp->CrypInCount++;
3581
3582 if (hcryp->CrypInCount == (hcryp->Size / 4U))
3583 {
3584 /* Call Input transfer complete callback */
3585#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3586 /*Call registered Input complete callback*/
3587 hcryp->InCpltCallback(hcryp);
3588#else
3589 /*Call legacy weak Input complete callback*/
3590 HAL_CRYP_InCpltCallback(hcryp);
3591#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3592 }
3593 }
3594#endif /* End AES or CRYP */
3595
3596 }
3597 else
3598 {
3599 /* Busy error code field */
3600 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
3601#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3602 /*Call registered error callback*/
3603 hcryp->ErrorCallback(hcryp);
3604#else
3605 /*Call legacy weak error callback*/
3606 HAL_CRYP_ErrorCallback(hcryp);
3607#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3608 }
3609}
3610
3618static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
3619{
3620#if defined (CRYP)
3621
3622 switch (KeySize)
3623 {
3624 case CRYP_KEYSIZE_256B:
3625 hcryp->Instance->K0LR = *(uint32_t *)(hcryp->Init.pKey);
3626 hcryp->Instance->K0RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3627 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3628 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3629 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 4);
3630 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 5);
3631 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 6);
3632 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 7);
3633 break;
3634 case CRYP_KEYSIZE_192B:
3635 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
3636 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3637 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3638 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3639 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
3640 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
3641 break;
3642 case CRYP_KEYSIZE_128B:
3643 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey);
3644 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3645 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3646 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3647
3648 break;
3649 default:
3650 break;
3651 }
3652#else /*AES*/
3653 switch (KeySize)
3654 {
3655 case CRYP_KEYSIZE_256B:
3656 hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
3657 hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1);
3658 hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2);
3659 hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3);
3660 hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4);
3661 hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5);
3662 hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6);
3663 hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7);
3664 break;
3665 case CRYP_KEYSIZE_128B:
3666 hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
3667 hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1);
3668 hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2);
3669 hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3);
3670
3671 break;
3672 default:
3673 break;
3674 }
3675#endif /* End AES or CRYP */
3676}
3677
3678#if defined (CRYP_CR_ALGOMODE_AES_GCM)|| defined (AES)
3686static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3687{
3688 uint32_t tickstart;
3689 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
3690 uint16_t outcount; /* Temporary CrypOutCount Value */
3691 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3692
3693 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3694 {
3695 if (hcryp->KeyIVConfig == 1U)
3696 {
3697 /* If the Key and IV configuration has to be done only once
3698 and if it has already been done, skip it */
3699 DoKeyIVConfig = 0U;
3700 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3701 }
3702 else
3703 {
3704 /* If the Key and IV configuration has to be done only once
3705 and if it has not been done already, do it and set KeyIVConfig
3706 to keep track it won't have to be done again next time */
3707 hcryp->KeyIVConfig = 1U;
3708 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3709 }
3710 }
3711 else
3712 {
3713 hcryp->SizesSum = hcryp->Size;
3714 }
3715
3716 if (DoKeyIVConfig == 1U)
3717 {
3718 /* Reset CrypHeaderCount */
3719 hcryp->CrypHeaderCount = 0U;
3720
3721 /****************************** Init phase **********************************/
3722
3723 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3724
3725 /* Set the key */
3726 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3727
3728#if defined(CRYP)
3729
3730 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3731 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3732 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3733 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3734 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3735
3736 /* Enable the CRYP peripheral */
3737 __HAL_CRYP_ENABLE(hcryp);
3738
3739 /* Get tick */
3740 tickstart = HAL_GetTick();
3741
3742 /*Wait for the CRYPEN bit to be cleared*/
3743 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
3744 {
3745 /* Check for the Timeout */
3746 if (Timeout != HAL_MAX_DELAY)
3747 {
3748 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3749 {
3750 /* Disable the CRYP peripheral clock */
3751 __HAL_CRYP_DISABLE(hcryp);
3752
3753 /* Change state */
3754 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3755 hcryp->State = HAL_CRYP_STATE_READY;
3756
3757 /* Process unlocked */
3758 __HAL_UNLOCK(hcryp);
3759 return HAL_ERROR;
3760 }
3761 }
3762 }
3763
3764#else /* AES */
3765 /* Workaround 1 : only AES.
3766 Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
3767 enabling the IP, datatype different from 32 bits can be configured.*/
3768 /* Select DATATYPE 32 */
3769 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
3770
3771 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3772 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3773 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3774 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3775 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3776
3777 /* Enable the CRYP peripheral */
3778 __HAL_CRYP_ENABLE(hcryp);
3779
3780 /* just wait for hash computation */
3781 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3782 {
3783 /* Change state */
3784 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3785 hcryp->State = HAL_CRYP_STATE_READY;
3786
3787 /* Process unlocked & return error */
3788 __HAL_UNLOCK(hcryp);
3789 return HAL_ERROR;
3790 }
3791 /* Clear CCF flag */
3792 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3793
3794#endif /* End AES or CRYP */
3795
3796 /************************ Header phase *************************************/
3797
3798 if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
3799 {
3800 return HAL_ERROR;
3801 }
3802
3803 /*************************Payload phase ************************************/
3804
3805 /* Set the phase */
3806 hcryp->Phase = CRYP_PHASE_PROCESS;
3807
3808#if defined(CRYP)
3809
3810 /* Disable the CRYP peripheral */
3811 __HAL_CRYP_DISABLE(hcryp);
3812
3813 /* Select payload phase once the header phase is performed */
3814 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3815
3816 /* Enable the CRYP peripheral */
3817 __HAL_CRYP_ENABLE(hcryp);
3818
3819#else /* AES */
3820
3821 /* Select payload phase once the header phase is performed */
3822 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3823
3824#endif /* End AES or CRYP */
3825 } /* if (DoKeyIVConfig == 1U) */
3826
3827 if ((hcryp->Size % 16U) != 0U)
3828 {
3829 /* recalculate wordsize */
3830 wordsize = ((wordsize / 4U) * 4U) ;
3831 }
3832
3833 /* Get tick */
3834 tickstart = HAL_GetTick();
3835 /*Temporary CrypOutCount Value*/
3836 outcount = hcryp->CrypOutCount;
3837
3838 /* Write input data and get output Data */
3839 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
3840 {
3841 /* Write plain data and get cipher data */
3842 CRYP_AES_ProcessData(hcryp, Timeout);
3843
3844 /*Temporary CrypOutCount Value*/
3845 outcount = hcryp->CrypOutCount;
3846
3847 /* Check for the Timeout */
3848 if (Timeout != HAL_MAX_DELAY)
3849 {
3850 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3851 {
3852 /* Disable the CRYP peripheral clock */
3853 __HAL_CRYP_DISABLE(hcryp);
3854
3855 /* Change state & error code */
3856 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3857 hcryp->State = HAL_CRYP_STATE_READY;
3858
3859 /* Process unlocked */
3860 __HAL_UNLOCK(hcryp);
3861 return HAL_ERROR;
3862 }
3863 }
3864 }
3865
3866 if ((hcryp->Size % 16U) != 0U)
3867 {
3868 /* Workaround 2 : CRYP1 & AES generates correct TAG for GCM mode only when input block size is multiple of
3869 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when GCM encryption
3870 is selected, then the TAG message will be wrong.*/
3871 CRYP_Workaround(hcryp, Timeout);
3872 }
3873
3874 /* Return function status */
3875 return HAL_OK;
3876}
3877
3884static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
3885{
3886 __IO uint32_t count = 0U;
3887 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3888#if defined(AES)
3889 uint32_t loopcounter;
3890 uint32_t lastwordsize;
3891 uint32_t npblb;
3892#endif /* AES */
3893
3894 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3895 {
3896 if (hcryp->KeyIVConfig == 1U)
3897 {
3898 /* If the Key and IV configuration has to be done only once
3899 and if it has already been done, skip it */
3900 DoKeyIVConfig = 0U;
3901 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3902 }
3903 else
3904 {
3905 /* If the Key and IV configuration has to be done only once
3906 and if it has not been done already, do it and set KeyIVConfig
3907 to keep track it won't have to be done again next time */
3908 hcryp->KeyIVConfig = 1U;
3909 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3910 }
3911 }
3912 else
3913 {
3914 hcryp->SizesSum = hcryp->Size;
3915 }
3916
3917 /* Configure Key, IV and process message (header and payload) */
3918 if (DoKeyIVConfig == 1U)
3919 {
3920 /* Reset CrypHeaderCount */
3921 hcryp->CrypHeaderCount = 0U;
3922
3923 /******************************* Init phase *********************************/
3924
3925 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3926
3927 /* Set the key */
3928 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3929
3930#if defined(CRYP)
3931 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3932 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3933 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3934 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3935 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3936
3937 /* Enable the CRYP peripheral */
3938 __HAL_CRYP_ENABLE(hcryp);
3939
3940 /*Wait for the CRYPEN bit to be cleared*/
3941 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3942 do
3943 {
3944 count-- ;
3945 if (count == 0U)
3946 {
3947 /* Disable the CRYP peripheral clock */
3948 __HAL_CRYP_DISABLE(hcryp);
3949
3950 /* Change state */
3951 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3952 hcryp->State = HAL_CRYP_STATE_READY;
3953
3954 /* Process unlocked */
3955 __HAL_UNLOCK(hcryp);
3956 return HAL_ERROR;
3957 }
3958 } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
3959
3960#else /* AES */
3961
3962 /* Workaround 1 : only AES
3963 Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re
3964 enabling the IP, datatype different from 32 bits can be configured.*/
3965 /* Select DATATYPE 32 */
3966 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
3967
3968 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3969 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3970 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3971 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3972 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3973
3974 /* Enable the CRYP peripheral */
3975 __HAL_CRYP_ENABLE(hcryp);
3976
3977 /* just wait for hash computation */
3978 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3979 do
3980 {
3981 count-- ;
3982 if (count == 0U)
3983 {
3984 /* Disable the CRYP peripheral clock */
3985 __HAL_CRYP_DISABLE(hcryp);
3986
3987 /* Change state */
3988 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3989 hcryp->State = HAL_CRYP_STATE_READY;
3990
3991 /* Process unlocked */
3992 __HAL_UNLOCK(hcryp);
3993 return HAL_ERROR;
3994 }
3995 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
3996
3997 /* Clear CCF flag */
3998 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3999
4000#endif /* End AES or CRYP */
4001
4002 /***************************** Header phase *********************************/
4003
4004#if defined(CRYP)
4005
4006 /* Select header phase */
4007 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4008
4009 /* Enable interrupts */
4010 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
4011
4012 /* Enable CRYP */
4013 __HAL_CRYP_ENABLE(hcryp);
4014
4015#else /* AES */
4016
4017 /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/
4018 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
4019
4020 /* Select header phase */
4021 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4022
4023 /* Enable computation complete flag and error interrupts */
4024 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
4025
4026 /* Enable the CRYP peripheral */
4027 __HAL_CRYP_ENABLE(hcryp);
4028
4029 if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
4030 {
4031 /* Set the phase */
4032 hcryp->Phase = CRYP_PHASE_PROCESS;
4033
4034 /* Select payload phase once the header phase is performed */
4035 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
4036
4037 /* Write the payload Input block in the IN FIFO */
4038 if (hcryp->Size == 0U)
4039 {
4040 /* Disable interrupts */
4041 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
4042
4043 /* Change the CRYP state */
4044 hcryp->State = HAL_CRYP_STATE_READY;
4045
4046 /* Process unlocked */
4047 __HAL_UNLOCK(hcryp);
4048 }
4049 else if (hcryp->Size >= 16U)
4050 {
4051 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4052 hcryp->CrypInCount++;
4053 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4054 hcryp->CrypInCount++;
4055 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4056 hcryp->CrypInCount++;
4057 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4058 hcryp->CrypInCount++;
4059 if (hcryp->CrypInCount == (hcryp->Size / 4U))
4060 {
4061 /* Call Input transfer complete callback */
4062#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4063 /*Call registered Input complete callback*/
4064 hcryp->InCpltCallback(hcryp);
4065#else
4066 /*Call legacy weak Input complete callback*/
4067 HAL_CRYP_InCpltCallback(hcryp);
4068#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4069 }
4070 }
4071 else /* Size < 16Bytes : first block is the last block*/
4072 {
4073 /* Workaround not implemented*/
4074 /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
4075 Workaround is implemented in polling mode, so if last block of
4076 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
4077
4078 /* Compute the number of padding bytes in last block of payload */
4079 npblb = 16U - (uint32_t)(hcryp->Size);
4080
4081 /* Number of valid words (lastwordsize) in last block */
4082 if ((npblb % 4U) == 0U)
4083 {
4084 lastwordsize = (16U - npblb) / 4U;
4085 }
4086 else
4087 {
4088 lastwordsize = ((16U - npblb) / 4U) + 1U;
4089 }
4090
4091 /* last block optionally pad the data with zeros*/
4092 for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
4093 {
4094 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4095 hcryp->CrypInCount++;
4096 }
4097 while (loopcounter < 4U)
4098 {
4099 /* pad the data with zeros to have a complete block */
4100 hcryp->Instance->DINR = 0x0U;
4101 loopcounter++;
4102 }
4103 }
4104 }
4105 else if ((hcryp->Init.HeaderSize) < 4U)
4106 {
4107 for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
4108 {
4109 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4110 hcryp->CrypHeaderCount++ ;
4111 }
4112 while (loopcounter < 4U)
4113 {
4114 /* pad the data with zeros to have a complete block */
4115 hcryp->Instance->DINR = 0x0U;
4116 loopcounter++;
4117 }
4118 /* Set the phase */
4119 hcryp->Phase = CRYP_PHASE_PROCESS;
4120
4121 /* Select payload phase once the header phase is performed */
4122 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4123
4124 /* Call Input transfer complete callback */
4125#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4126 /*Call registered Input complete callback*/
4127 hcryp->InCpltCallback(hcryp);
4128#else
4129 /*Call legacy weak Input complete callback*/
4130 HAL_CRYP_InCpltCallback(hcryp);
4131#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4132 }
4133 else if ((hcryp->Init.HeaderSize) >= 4U)
4134 {
4135 /* Write the input block in the IN FIFO */
4136 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4137 hcryp->CrypHeaderCount++;
4138 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4139 hcryp->CrypHeaderCount++;
4140 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4141 hcryp->CrypHeaderCount++;
4142 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4143 hcryp->CrypHeaderCount++;
4144 }
4145 else
4146 {
4147 /* Nothing to do */
4148 }
4149
4150#endif /* End AES or CRYP */
4151 } /* end of if (DoKeyIVConfig == 1U) */
4152
4153 /* Return function status */
4154 return HAL_OK;
4155}
4156
4157
4164static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
4165{
4166 __IO uint32_t count = 0U;
4167 uint32_t wordsize;
4168 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4169
4170 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4171 {
4172 if (hcryp->KeyIVConfig == 1U)
4173 {
4174 /* If the Key and IV configuration has to be done only once
4175 and if it has already been done, skip it */
4176 DoKeyIVConfig = 0U;
4177 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4178 }
4179 else
4180 {
4181 /* If the Key and IV configuration has to be done only once
4182 and if it has not been done already, do it and set KeyIVConfig
4183 to keep track it won't have to be done again next time */
4184 hcryp->KeyIVConfig = 1U;
4185 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4186 }
4187 }
4188 else
4189 {
4190 hcryp->SizesSum = hcryp->Size;
4191 }
4192
4193 if (DoKeyIVConfig == 1U)
4194 {
4195 /* Reset CrypHeaderCount */
4196 hcryp->CrypHeaderCount = 0U;
4197
4198 /*************************** Init phase ************************************/
4199
4200 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4201
4202 /* Set the key */
4203 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4204
4205#if defined(CRYP)
4206 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4207 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
4208 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4209 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4210 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4211
4212 /* Enable the CRYP peripheral */
4213 __HAL_CRYP_ENABLE(hcryp);
4214
4215 /*Wait for the CRYPEN bit to be cleared*/
4216 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4217 do
4218 {
4219 count-- ;
4220 if (count == 0U)
4221 {
4222 /* Disable the CRYP peripheral clock */
4223 __HAL_CRYP_DISABLE(hcryp);
4224
4225 /* Change state */
4226 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4227 hcryp->State = HAL_CRYP_STATE_READY;
4228
4229 /* Process unlocked */
4230 __HAL_UNLOCK(hcryp);
4231 return HAL_ERROR;
4232 }
4233 } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
4234
4235#else /* AES */
4236
4237 /*Workaround 1 : only AES
4238 Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
4239 enabling the IP, datatype different from 32 bits can be configured.*/
4240 /* Select DATATYPE 32 */
4241 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
4242
4243 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4244 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
4245 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4246 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4247 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4248
4249 /* Enable the CRYP peripheral */
4250 __HAL_CRYP_ENABLE(hcryp);
4251
4252 /* just wait for hash computation */
4253 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4254 do
4255 {
4256 count-- ;
4257 if (count == 0U)
4258 {
4259 /* Disable the CRYP peripheral clock */
4260 __HAL_CRYP_DISABLE(hcryp);
4261
4262 /* Change state */
4263 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4264 hcryp->State = HAL_CRYP_STATE_READY;
4265
4266 /* Process unlocked */
4267 __HAL_UNLOCK(hcryp);
4268 return HAL_ERROR;
4269 }
4270 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
4271
4272 /* Clear CCF flag */
4273 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4274
4275#endif /* End AES or CRYP */
4276
4277 /************************ Header phase *************************************/
4278
4279 if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
4280 {
4281 return HAL_ERROR;
4282 }
4283
4284 /************************ Payload phase ************************************/
4285
4286 /* Set the phase */
4287 hcryp->Phase = CRYP_PHASE_PROCESS;
4288
4289#if defined(CRYP)
4290
4291 /* Disable the CRYP peripheral */
4292 __HAL_CRYP_DISABLE(hcryp);
4293
4294#endif /* CRYP */
4295
4296 /* Select payload phase once the header phase is performed */
4297 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4298
4299 } /* if (DoKeyIVConfig == 1U) */
4300
4301 if (hcryp->Size != 0U)
4302 {
4303 /* CRYP1 IP V < 2.2.1 Size should be %4 otherwise Tag will
4304 be incorrectly generated for GCM Encryption:
4305 Workaround is implemented in polling mode, so if last block of
4306 payload <128bit don't use DMA mode otherwise TAG is incorrectly generated . */
4307 /* Set the input and output addresses and start DMA transfer */
4308 if ((hcryp->Size % 16U) == 0U)
4309 {
4310 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U),
4311 (uint32_t)(hcryp->pCrypOutBuffPtr));
4312 }
4313 else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
4314 {
4315 wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ;
4316
4317 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
4318 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U),
4319 (uint32_t)(hcryp->pCrypOutBuffPtr));
4320 }
4321 }
4322 else
4323 {
4324 /* Process unLocked */
4325 __HAL_UNLOCK(hcryp);
4326
4327 /* Change the CRYP state and phase */
4328 hcryp->State = HAL_CRYP_STATE_READY;
4329 }
4330
4331 /* Return function status */
4332 return HAL_OK;
4333}
4334
4335
4344static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
4345{
4346 uint32_t tickstart;
4347 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
4348 uint16_t outcount; /* Temporary CrypOutCount Value */
4349 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4350#if defined(AES)
4351 uint32_t loopcounter;
4352 uint32_t npblb;
4353 uint32_t lastwordsize;
4354#endif /* AES */
4355
4356 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4357 {
4358 if (hcryp->KeyIVConfig == 1U)
4359 {
4360 /* If the Key and IV configuration has to be done only once
4361 and if it has already been done, skip it */
4362 DoKeyIVConfig = 0U;
4363 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4364 }
4365 else
4366 {
4367 /* If the Key and IV configuration has to be done only once
4368 and if it has not been done already, do it and set KeyIVConfig
4369 to keep track it won't have to be done again next time */
4370 hcryp->KeyIVConfig = 1U;
4371 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4372 }
4373 }
4374 else
4375 {
4376 hcryp->SizesSum = hcryp->Size;
4377 }
4378
4379 if (DoKeyIVConfig == 1U)
4380 {
4381
4382 /* Reset CrypHeaderCount */
4383 hcryp->CrypHeaderCount = 0U;
4384
4385#if defined(CRYP)
4386
4387 /********************** Init phase ******************************************/
4388
4389 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4390
4391 /* Set the key */
4392 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4393
4394 /* Set the initialization vector (IV) with CTR1 information */
4395 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4396 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4397 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4398 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
4399
4400
4401 /* Enable the CRYP peripheral */
4402 __HAL_CRYP_ENABLE(hcryp);
4403
4404 /*Write B0 packet into CRYP_DIN Register*/
4405 if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4406 {
4407 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
4408 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
4409 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
4410 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
4411 }
4412 else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4413 {
4414 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
4415 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
4416 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
4417 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
4418 }
4419 else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
4420 {
4421 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
4422 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
4423 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
4424 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
4425 }
4426 else
4427 {
4428 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
4429 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
4430 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
4431 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
4432 }
4433 /* Get tick */
4434 tickstart = HAL_GetTick();
4435
4436 /*Wait for the CRYPEN bit to be cleared*/
4437 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
4438 {
4439 /* Check for the Timeout */
4440 if (Timeout != HAL_MAX_DELAY)
4441 {
4442 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4443 {
4444 /* Disable the CRYP peripheral clock */
4445 __HAL_CRYP_DISABLE(hcryp);
4446
4447 /* Change state */
4448 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4449 hcryp->State = HAL_CRYP_STATE_READY;
4450
4451 /* Process unlocked */
4452 __HAL_UNLOCK(hcryp);
4453 return HAL_ERROR;
4454 }
4455 }
4456 }
4457#else /* AES */
4458 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
4459 /* Select header phase */
4460 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4461
4462 /* configured encryption mode */
4463 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
4464
4465 /* Set the key */
4466 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4467
4468 /* Set the initialization vector with zero values*/
4469 hcryp->Instance->IVR3 = 0U;
4470 hcryp->Instance->IVR2 = 0U;
4471 hcryp->Instance->IVR1 = 0U;
4472 hcryp->Instance->IVR0 = 0U;
4473
4474 /* Enable the CRYP peripheral */
4475 __HAL_CRYP_ENABLE(hcryp);
4476
4477 /*Write the B0 packet into CRYP_DIN*/
4478 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
4479 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
4480 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
4481 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
4482
4483 /* wait until the end of computation */
4484 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4485 {
4486 /* Change state */
4487 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4488 hcryp->State = HAL_CRYP_STATE_READY;
4489
4490 /* Process unlocked & return error */
4491 __HAL_UNLOCK(hcryp);
4492 return HAL_ERROR;
4493 }
4494 /* Clear CCF flag */
4495 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4496
4497 /* Set the phase */
4498 hcryp->Phase = CRYP_PHASE_PROCESS;
4499
4500 /* From that point the whole message must be processed, first the Header then the payload.
4501 First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
4502
4503 if (hcryp->Init.HeaderSize != 0U)
4504 {
4505 if ((hcryp->Init.HeaderSize % 4U) == 0U)
4506 {
4507 /* HeaderSize %4, no padding */
4508 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
4509 {
4510 /* Write the Input block in the Data Input register */
4511 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4512 hcryp->CrypHeaderCount++ ;
4513 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4514 hcryp->CrypHeaderCount++ ;
4515 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4516 hcryp->CrypHeaderCount++ ;
4517 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4518 hcryp->CrypHeaderCount++ ;
4519
4520 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4521 {
4522 /* Disable the CRYP peripheral clock */
4523 __HAL_CRYP_DISABLE(hcryp);
4524
4525 /* Change state */
4526 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4527 hcryp->State = HAL_CRYP_STATE_READY;
4528
4529 /* Process unlocked */
4530 __HAL_UNLOCK(hcryp);
4531 return HAL_ERROR;
4532 }
4533 /* Clear CCF Flag */
4534 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4535 }
4536 }
4537 else
4538 {
4539 /*Write Header block in the IN FIFO without last block */
4540 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U)));
4541 loopcounter += 4U)
4542 {
4543 /* Write the input block in the data input register */
4544 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4545 hcryp->CrypHeaderCount++ ;
4546 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4547 hcryp->CrypHeaderCount++ ;
4548 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4549 hcryp->CrypHeaderCount++ ;
4550 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4551 hcryp->CrypHeaderCount++ ;
4552
4553 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4554 {
4555 /* Disable the CRYP peripheral clock */
4556 __HAL_CRYP_DISABLE(hcryp);
4557
4558 /* Change state */
4559 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4560 hcryp->State = HAL_CRYP_STATE_READY;
4561
4562 /* Process unlocked */
4563 __HAL_UNLOCK(hcryp);
4564 return HAL_ERROR;
4565 }
4566 /* Clear CCF Flag */
4567 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4568 }
4569 /* Last block optionally pad the data with zeros*/
4570 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
4571 {
4572 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4573 hcryp->CrypHeaderCount++ ;
4574 }
4575 while (loopcounter < 4U)
4576 {
4577 /* Pad the data with zeros to have a complete block */
4578 hcryp->Instance->DINR = 0x0U;
4579 loopcounter++;
4580 }
4581
4582 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4583 {
4584 /* Disable the CRYP peripheral clock */
4585 __HAL_CRYP_DISABLE(hcryp);
4586
4587 /* Change state */
4588 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4589 hcryp->State = HAL_CRYP_STATE_READY;
4590
4591 /* Process unlocked */
4592 __HAL_UNLOCK(hcryp);
4593 return HAL_ERROR;
4594 }
4595 /* Clear CCF flag */
4596 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4597 }
4598 }
4599 } /* if (DoKeyIVConfig == 1U) */
4600 /* Then the payload: cleartext payload (not the ciphertext payload).
4601 Write input Data, no output Data to get */
4602 if (hcryp->Size != 0U)
4603 {
4604 if ((hcryp->Size % 16U) != 0U)
4605 {
4606 /* recalculate wordsize */
4607 wordsize = ((wordsize / 4U) * 4U) ;
4608 }
4609
4610 /* Get tick */
4611 tickstart = HAL_GetTick();
4612 /*Temporary CrypOutCount Value*/
4613 outcount = hcryp->CrypOutCount;
4614
4615 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
4616 {
4617 /* Write plain data and get cipher data */
4618 CRYP_AES_ProcessData(hcryp, Timeout);
4619
4620 /*Temporary CrypOutCount Value*/
4621 outcount = hcryp->CrypOutCount;
4622
4623 /* Check for the Timeout */
4624 if (Timeout != HAL_MAX_DELAY)
4625 {
4626 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4627 {
4628 /* Disable the CRYP peripheral clock */
4629 __HAL_CRYP_DISABLE(hcryp);
4630
4631 /* Change state */
4632 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4633 hcryp->State = HAL_CRYP_STATE_READY;
4634
4635 /* Process unlocked */
4636 __HAL_UNLOCK(hcryp);
4637 return HAL_ERROR;
4638 }
4639 }
4640 }
4641
4642 if ((hcryp->Size % 16U) != 0U)
4643 {
4644 /* Compute the number of padding bytes in last block of payload */
4645 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
4646
4647 /* Number of valid words (lastwordsize) in last block */
4648 if ((npblb % 4U) == 0U)
4649 {
4650 lastwordsize = (16U - npblb) / 4U;
4651 }
4652 else
4653 {
4654 lastwordsize = ((16U - npblb) / 4U) + 1U;
4655 }
4656 /* Last block optionally pad the data with zeros*/
4657 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
4658 {
4659 /* Write the last input block in the IN FIFO */
4660 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4661 hcryp->CrypInCount++;
4662 }
4663 while (loopcounter < 4U)
4664 {
4665 /* Pad the data with zeros to have a complete block */
4666 hcryp->Instance->DINR = 0U;
4667 loopcounter++;
4668 }
4669 /* Wait for CCF flag to be raised */
4670 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4671 {
4672 /* Disable the CRYP peripheral clock */
4673 __HAL_CRYP_DISABLE(hcryp);
4674
4675 /* Change state */
4676 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4677 hcryp->State = HAL_CRYP_STATE_READY;
4678
4679 /* Process unlocked */
4680 __HAL_UNLOCK(hcryp);
4681 return HAL_ERROR;
4682 }
4683 /* Clear CCF flag */
4684 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4685
4686 }
4687 }
4688#endif /* End AES or CRYP */
4689
4690#if defined(CRYP)
4691
4692 /************************* Header phase *************************************/
4693 /* Header block(B1) : associated data length expressed in bytes concatenated
4694 with Associated Data (A)*/
4695
4696 if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
4697 {
4698 return HAL_ERROR;
4699 }
4700
4701 /********************** Payload phase ***************************************/
4702
4703 /* Set the phase */
4704 hcryp->Phase = CRYP_PHASE_PROCESS;
4705
4706 /* Disable the CRYP peripheral */
4707 __HAL_CRYP_DISABLE(hcryp);
4708
4709 /* Select payload phase once the header phase is performed */
4710 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4711
4712 /* Enable the CRYP peripheral */
4713 __HAL_CRYP_ENABLE(hcryp);
4714
4715 } /* if (DoKeyIVConfig == 1U) */
4716
4717 if ((hcryp->Size % 16U) != 0U)
4718 {
4719 /* recalculate wordsize */
4720 wordsize = ((wordsize / 4U) * 4U) ;
4721 }
4722 /* Get tick */
4723 tickstart = HAL_GetTick();
4724 /*Temporary CrypOutCount Value*/
4725 outcount = hcryp->CrypOutCount;
4726
4727 /* Write input data and get output data */
4728 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
4729 {
4730 /* Write plain data and get cipher data */
4731 CRYP_AES_ProcessData(hcryp, Timeout);
4732
4733 /* Check for the Timeout */
4734 if (Timeout != HAL_MAX_DELAY)
4735 {
4736 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4737 {
4738 /* Disable the CRYP peripheral clock */
4739 __HAL_CRYP_DISABLE(hcryp);
4740
4741 /* Change state */
4742 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4743 hcryp->State = HAL_CRYP_STATE_READY;
4744
4745 /* Process unlocked */
4746 __HAL_UNLOCK(hcryp);
4747 return HAL_ERROR;
4748 }
4749 }
4750 }
4751
4752 if ((hcryp->Size % 16U) != 0U)
4753 {
4754 /* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption
4755 only when ciphertext blocks size is multiple of 128 bits. If lthe size of
4756 the last block of payload is inferior to 128 bits, when CCM decryption
4757 is selected, then the TAG message will be wrong.*/
4758 CRYP_Workaround(hcryp, Timeout);
4759 }
4760#endif /* CRYP */
4761
4762 /* Return function status */
4763 return HAL_OK;
4764}
4765
4773static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
4774{
4775 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4776#if defined(CRYP)
4777 __IO uint32_t count = 0U;
4778#endif /* CRYP */
4779
4780 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4781 {
4782 if (hcryp->KeyIVConfig == 1U)
4783 {
4784 /* If the Key and IV configuration has to be done only once
4785 and if it has already been done, skip it */
4786 DoKeyIVConfig = 0U;
4787 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4788 }
4789 else
4790 {
4791 /* If the Key and IV configuration has to be done only once
4792 and if it has not been done already, do it and set KeyIVConfig
4793 to keep track it won't have to be done again next time */
4794 hcryp->KeyIVConfig = 1U;
4795 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4796 }
4797 }
4798 else
4799 {
4800 hcryp->SizesSum = hcryp->Size;
4801 }
4802
4803 /* Configure Key, IV and process message (header and payload) */
4804 if (DoKeyIVConfig == 1U)
4805 {
4806 /* Reset CrypHeaderCount */
4807 hcryp->CrypHeaderCount = 0U;
4808
4809#if defined(CRYP)
4810
4811 /************ Init phase ************/
4812
4813 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4814
4815 /* Set the key */
4816 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4817
4818 /* Set the initialization vector (IV) with CTR1 information */
4819 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4820 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4821 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4822 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
4823
4824 /* Enable the CRYP peripheral */
4825 __HAL_CRYP_ENABLE(hcryp);
4826
4827 /*Write the B0 packet into CRYP_DIN Register*/
4828 if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4829 {
4830 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
4831 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
4832 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
4833 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
4834 }
4835 else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4836 {
4837 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
4838 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
4839 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
4840 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
4841 }
4842 else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
4843 {
4844 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
4845 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
4846 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
4847 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
4848 }
4849 else
4850 {
4851 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
4852 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
4853 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
4854 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
4855 }
4856 /*Wait for the CRYPEN bit to be cleared*/
4857 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4858 do
4859 {
4860 count-- ;
4861 if (count == 0U)
4862 {
4863 /* Disable the CRYP peripheral clock */
4864 __HAL_CRYP_DISABLE(hcryp);
4865
4866 /* Change state */
4867 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4868 hcryp->State = HAL_CRYP_STATE_READY;
4869
4870 /* Process unlocked */
4871 __HAL_UNLOCK(hcryp);
4872 return HAL_ERROR;
4873 }
4874 } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
4875
4876 /* Select header phase */
4877 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4878
4879 } /* end of if (DoKeyIVConfig == 1U) */
4880
4881 /* Enable interrupts */
4882 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
4883
4884 /* Enable CRYP */
4885 __HAL_CRYP_ENABLE(hcryp);
4886
4887#else /* AES */
4888
4889 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
4890 /* Select header phase */
4891 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4892
4893 /* configured mode and encryption mode */
4894 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
4895
4896 /* Set the key */
4897 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4898
4899 /* Set the initialization vector with zero values*/
4900 hcryp->Instance->IVR3 = 0U;
4901 hcryp->Instance->IVR2 = 0U;
4902 hcryp->Instance->IVR1 = 0U;
4903 hcryp->Instance->IVR0 = 0U;
4904
4905 /* Enable interrupts */
4906 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
4907 /* Enable the CRYP peripheral */
4908 __HAL_CRYP_ENABLE(hcryp);
4909
4910 /*Write the B0 packet into CRYP_DIN*/
4911 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
4912 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
4913 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
4914 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
4915
4916 } /* end of if (DoKeyIVConfig == 1U) */
4917#endif /* End AES or CRYP */
4918
4919 /* Return function status */
4920 return HAL_OK;
4921}
4929static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
4930{
4931 uint32_t wordsize;
4932 __IO uint32_t count = 0U;
4933 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4934#if defined(AES)
4935 uint32_t loopcounter;
4936 uint32_t npblb;
4937 uint32_t lastwordsize;
4938#endif /* AES */
4939
4940 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4941 {
4942 if (hcryp->KeyIVConfig == 1U)
4943 {
4944 /* If the Key and IV configuration has to be done only once
4945 and if it has already been done, skip it */
4946 DoKeyIVConfig = 0U;
4947 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4948 }
4949 else
4950 {
4951 /* If the Key and IV configuration has to be done only once
4952 and if it has not been done already, do it and set KeyIVConfig
4953 to keep track it won't have to be done again next time */
4954 hcryp->KeyIVConfig = 1U;
4955 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4956 }
4957 }
4958 else
4959 {
4960 hcryp->SizesSum = hcryp->Size;
4961 }
4962
4963 if (DoKeyIVConfig == 1U)
4964 {
4965
4966 /* Reset CrypHeaderCount */
4967 hcryp->CrypHeaderCount = 0U;
4968
4969#if defined(CRYP)
4970
4971 /************************** Init phase **************************************/
4972
4973 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4974
4975 /* Set the key */
4976 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4977
4978 /* Set the initialization vector (IV) with CTR1 information */
4979 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4980 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4981 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4982 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
4983
4984 /* Enable the CRYP peripheral */
4985 __HAL_CRYP_ENABLE(hcryp);
4986
4987 /*Write the B0 packet into CRYP_DIN Register*/
4988 if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4989 {
4990 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
4991 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
4992 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
4993 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
4994 }
4995 else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4996 {
4997 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
4998 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
4999 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
5000 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
5001 }
5002 else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
5003 {
5004 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
5005 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
5006 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
5007 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
5008 }
5009 else
5010 {
5011 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
5012 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
5013 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
5014 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
5015 }
5016
5017 /*Wait for the CRYPEN bit to be cleared*/
5018 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5019 do
5020 {
5021 count-- ;
5022 if (count == 0U)
5023 {
5024 /* Disable the CRYP peripheral clock */
5025 __HAL_CRYP_DISABLE(hcryp);
5026
5027 /* Change state */
5028 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5029 hcryp->State = HAL_CRYP_STATE_READY;
5030
5031 /* Process unlocked */
5032 __HAL_UNLOCK(hcryp);
5033 return HAL_ERROR;
5034 }
5035 } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
5036
5037#else /* AES */
5038
5039 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
5040 /* Select header phase */
5041 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5042
5043 /* configured encryption mode */
5044 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
5045
5046 /* Set the key */
5047 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5048
5049 /* Set the initialization vector with zero values*/
5050 hcryp->Instance->IVR3 = 0U;
5051 hcryp->Instance->IVR2 = 0U;
5052 hcryp->Instance->IVR1 = 0U;
5053 hcryp->Instance->IVR0 = 0U;
5054
5055 /* Enable the CRYP peripheral */
5056 __HAL_CRYP_ENABLE(hcryp);
5057
5058 /*Write the B0 packet into CRYP_DIN*/
5059 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
5060 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
5061 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
5062 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
5063
5064 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5065 do
5066 {
5067 count-- ;
5068 if (count == 0U)
5069 {
5070 /* Disable the CRYP peripheral clock */
5071 __HAL_CRYP_DISABLE(hcryp);
5072
5073 /* Change state */
5074 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5075 hcryp->State = HAL_CRYP_STATE_READY;
5076
5077 /* Process Unlocked */
5078 __HAL_UNLOCK(hcryp);
5079 return HAL_ERROR;
5080 }
5081 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5082 /* Clear CCF flag */
5083 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5084
5085 /* Set the phase */
5086 hcryp->Phase = CRYP_PHASE_PROCESS;
5087
5088 /* From that point the whole message must be processed, first the Header then the payload.
5089 First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
5090
5091 if (hcryp->Init.HeaderSize != 0U)
5092 {
5093 if ((hcryp->Init.HeaderSize % 4U) == 0U)
5094 {
5095 /* HeaderSize %4, no padding */
5096 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
5097 {
5098 /* Write the Input block in the Data Input register */
5099 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5100 hcryp->CrypHeaderCount++ ;
5101 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5102 hcryp->CrypHeaderCount++ ;
5103 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5104 hcryp->CrypHeaderCount++ ;
5105 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5106 hcryp->CrypHeaderCount++ ;
5107
5108 /* wait until the end of computation */
5109 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5110 do
5111 {
5112 count-- ;
5113 if (count == 0U)
5114 {
5115 /* Disable the CRYP peripheral clock */
5116 __HAL_CRYP_DISABLE(hcryp);
5117
5118 /* Change state */
5119 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5120 hcryp->State = HAL_CRYP_STATE_READY;
5121
5122 /* Process Unlocked */
5123 __HAL_UNLOCK(hcryp);
5124 return HAL_ERROR;
5125 }
5126 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5127 /* Clear CCF flag */
5128 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5129 }
5130 }
5131 else
5132 {
5133 /*Write Header block in the IN FIFO without last block */
5134 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U)));
5135 loopcounter += 4U)
5136 {
5137 /* Write the input block in the data input register */
5138 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5139 hcryp->CrypHeaderCount++ ;
5140 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5141 hcryp->CrypHeaderCount++ ;
5142 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5143 hcryp->CrypHeaderCount++ ;
5144 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5145 hcryp->CrypHeaderCount++ ;
5146
5147 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5148 do
5149 {
5150 count-- ;
5151 if (count == 0U)
5152 {
5153 /* Disable the CRYP peripheral clock */
5154 __HAL_CRYP_DISABLE(hcryp);
5155
5156 /* Change state */
5157 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5158 hcryp->State = HAL_CRYP_STATE_READY;
5159
5160 /* Process Unlocked */
5161 __HAL_UNLOCK(hcryp);
5162 return HAL_ERROR;
5163 }
5164 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5165 /* Clear CCF flag */
5166 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5167 }
5168 /* Last block optionally pad the data with zeros*/
5169 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
5170 {
5171 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5172 hcryp->CrypHeaderCount++ ;
5173 }
5174 while (loopcounter < 4U)
5175 {
5176 /* Pad the data with zeros to have a complete block */
5177 hcryp->Instance->DINR = 0x0U;
5178 loopcounter++;
5179 }
5180
5181 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5182 do
5183 {
5184 count-- ;
5185 if (count == 0U)
5186 {
5187 /* Disable the CRYP peripheral clock */
5188 __HAL_CRYP_DISABLE(hcryp);
5189
5190 /* Change state */
5191 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5192 hcryp->State = HAL_CRYP_STATE_READY;
5193
5194 /* Process Unlocked */
5195 __HAL_UNLOCK(hcryp);
5196 return HAL_ERROR;
5197 }
5198 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5199 /* Clear CCF flag */
5200 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5201 }
5202 }
5203 } /* if (DoKeyIVConfig == 1U) */
5204 /* Then the payload: cleartext payload (not the ciphertext payload).
5205 Write input Data, no output Data to get */
5206 if (hcryp->Size != 0U)
5207 {
5208 if (hcryp->Size >= 16U)
5209 {
5210 if ((hcryp->Size % 16U) == 0U)
5211 {
5212 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U),
5213 (uint32_t)(hcryp->pCrypOutBuffPtr));
5214 }
5215 else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
5216 {
5217 wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ;
5218
5219 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
5220 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U),
5221 (uint32_t)(hcryp->pCrypOutBuffPtr));
5222 }
5223 }
5224 if ((hcryp->Size < 16U) != 0U)
5225 {
5226 /* Compute the number of padding bytes in last block of payload */
5227 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5228
5229 /* Number of valid words (lastwordsize) in last block */
5230 if ((npblb % 4U) == 0U)
5231 {
5232 lastwordsize = (16U - npblb) / 4U;
5233 }
5234 else
5235 {
5236 lastwordsize = ((16U - npblb) / 4U) + 1U;
5237 }
5238 /* Last block optionally pad the data with zeros*/
5239 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
5240 {
5241 /* Write the last input block in the IN FIFO */
5242 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5243 hcryp->CrypInCount++;
5244 }
5245 while (loopcounter < 4U)
5246 {
5247 /* Pad the data with zeros to have a complete block */
5248 hcryp->Instance->DINR = 0U;
5249 loopcounter++;
5250 }
5251 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5252 do
5253 {
5254 count-- ;
5255 if (count == 0U)
5256 {
5257 /* Disable the CRYP peripheral clock */
5258 __HAL_CRYP_DISABLE(hcryp);
5259
5260 /* Change state */
5261 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5262 hcryp->State = HAL_CRYP_STATE_READY;
5263
5264 /* Process Unlocked */
5265 __HAL_UNLOCK(hcryp);
5266 return HAL_ERROR;
5267 }
5268 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5269 /* Clear CCF flag */
5270 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5271
5272 /* Process unlocked */
5273 __HAL_UNLOCK(hcryp);
5274
5275 /* Change the CRYP state and phase */
5276 hcryp->State = HAL_CRYP_STATE_READY;
5277 }
5278 }
5279 else
5280 {
5281 /* Process unLocked */
5282 __HAL_UNLOCK(hcryp);
5283
5284 /* Change the CRYP state and phase */
5285 hcryp->State = HAL_CRYP_STATE_READY;
5286 }
5287#endif /* AES */
5288#if defined(CRYP)
5289 /********************* Header phase *****************************************/
5290
5291 if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
5292 {
5293 return HAL_ERROR;
5294 }
5295
5296 /******************** Payload phase *****************************************/
5297
5298 /* Set the phase */
5299 hcryp->Phase = CRYP_PHASE_PROCESS;
5300
5301 /* Disable the CRYP peripheral */
5302 __HAL_CRYP_DISABLE(hcryp);
5303
5304 /* Select payload phase once the header phase is performed */
5305 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
5306
5307 } /* if (DoKeyIVConfig == 1U) */
5308 if (hcryp->Size != 0U)
5309 {
5310 /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption
5311 Workaround is implemented in polling mode, so if last block of
5312 payload <128bit don't use HAL_CRYP_AESGCM_DMA otherwise TAG is incorrectly generated for GCM Encryption. */
5313 /* Set the input and output addresses and start DMA transfer */
5314 if ((hcryp->Size % 16U) == 0U)
5315 {
5316 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size / 4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
5317 }
5318 else
5319 {
5320 wordsize = (uint32_t)(hcryp->Size) + 16U - ((uint32_t)(hcryp->Size) % 16U) ;
5321
5322 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/
5323 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize / 4U,
5324 (uint32_t)(hcryp->pCrypOutBuffPtr));
5325 }
5326 }
5327 else /*Size = 0*/
5328 {
5329 /* Process unlocked */
5330 __HAL_UNLOCK(hcryp);
5331
5332 /* Change the CRYP state and phase */
5333 hcryp->State = HAL_CRYP_STATE_READY;
5334 }
5335#endif /* CRYP */
5336 /* Return function status */
5337 return HAL_OK;
5338}
5339
5346static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
5347{
5348 uint32_t loopcounter;
5349 uint32_t temp[4]; /* Temporary CrypOutBuff */
5350 uint32_t lastwordsize;
5351 uint32_t npblb;
5352 uint32_t i;
5353#if defined(AES)
5354 uint16_t outcount; /* Temporary CrypOutCount Value */
5355#endif /* AES */
5356
5357 /***************************** Payload phase *******************************/
5358
5359#if defined(CRYP)
5360 if (hcryp->Size == 0U)
5361 {
5362 /* Disable interrupts */
5363 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
5364
5365 /* Process unlocked */
5366 __HAL_UNLOCK(hcryp);
5367
5368 /* Change the CRYP state */
5369 hcryp->State = HAL_CRYP_STATE_READY;
5370 }
5371
5372 else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
5373 {
5374 /* Write the input block in the IN FIFO */
5375 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5376 hcryp->CrypInCount++;
5377 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5378 hcryp->CrypInCount++;
5379 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5380 hcryp->CrypInCount++;
5381 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5382 hcryp->CrypInCount++;
5383 if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U))
5384 {
5385 /* Disable interrupts */
5386 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
5387
5388 /* Call the input data transfer complete callback */
5389#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5390 /*Call registered Input complete callback*/
5391 hcryp->InCpltCallback(hcryp);
5392#else
5393 /*Call legacy weak Input complete callback*/
5394 HAL_CRYP_InCpltCallback(hcryp);
5395#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5396 }
5397 if (hcryp->CrypOutCount < (hcryp->Size / 4U))
5398 {
5399 /* Read the output block from the Output FIFO and put them in temporary buffer
5400 then get CrypOutBuff from temporary buffer */
5401 for (i = 0U; i < 4U; i++)
5402 {
5403 temp[i] = hcryp->Instance->DOUT;
5404 }
5405 i = 0U;
5406 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
5407 {
5408 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5409 hcryp->CrypOutCount++;
5410 i++;
5411 }
5412 if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U))
5413 {
5414 /* Disable interrupts */
5415 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
5416
5417 /* Change the CRYP state */
5418 hcryp->State = HAL_CRYP_STATE_READY;
5419
5420 /* Disable CRYP */
5421 __HAL_CRYP_DISABLE(hcryp);
5422
5423 /* Process unlocked */
5424 __HAL_UNLOCK(hcryp);
5425
5426 /* Call output transfer complete callback */
5427#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5428 /*Call registered Output complete callback*/
5429 hcryp->OutCpltCallback(hcryp);
5430#else
5431 /*Call legacy weak Output complete callback*/
5432 HAL_CRYP_OutCpltCallback(hcryp);
5433#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5434 }
5435 }
5436 }
5437 else if ((hcryp->Size % 16U) != 0U)
5438 {
5439 /* Size should be %4 in word and %16 in byte otherwise TAG will
5440 be incorrectly generated for GCM Encryption & CCM Decryption
5441 Workaround is implemented in polling mode, so if last block of
5442 payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */
5443
5444 /* Compute the number of padding bytes in last block of payload */
5445 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5446
5447 /* Number of valid words (lastwordsize) in last block */
5448 if ((npblb % 4U) == 0U)
5449 {
5450 lastwordsize = (16U - npblb) / 4U;
5451 }
5452 else
5453 {
5454 lastwordsize = ((16U - npblb) / 4U) + 1U;
5455 }
5456
5457 /* Last block optionally pad the data with zeros*/
5458 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
5459 {
5460 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5461 hcryp->CrypInCount++;
5462 }
5463 while (loopcounter < 4U)
5464 {
5465 /* Pad the data with zeros to have a complete block */
5466 hcryp->Instance->DIN = 0x0U;
5467 loopcounter++;
5468 }
5469 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
5470
5471 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
5472 {
5473 for (i = 0U; i < 4U; i++)
5474 {
5475 temp[i] = hcryp->Instance->DOUT;
5476 }
5477 if (((hcryp->Size) / 4U) == 0U)
5478 {
5479 for (i = 0U; i < ((uint32_t)(hcryp->Size) % 4U); i++)
5480 {
5481 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5482 hcryp->CrypOutCount++;
5483 }
5484 }
5485 i = 0x0U;
5486 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
5487 {
5488 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5489 hcryp->CrypOutCount++;
5490 i++;
5491 }
5492 }
5493 if (hcryp->CrypOutCount >= (hcryp->Size / 4U))
5494 {
5495 /* Disable interrupts */
5496 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI);
5497
5498 /* Change the CRYP peripheral state */
5499 hcryp->State = HAL_CRYP_STATE_READY;
5500
5501 /* Process unlocked */
5502 __HAL_UNLOCK(hcryp);
5503
5504 /* Call output transfer complete callback */
5505#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5506 /*Call registered Output complete callback*/
5507 hcryp->OutCpltCallback(hcryp);
5508#else
5509 /*Call legacy weak Output complete callback*/
5510 HAL_CRYP_OutCpltCallback(hcryp);
5511#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5512 }
5513 }
5514 else
5515 {
5516 /* Nothing to do */
5517 }
5518#else /* AES */
5519
5520 /* Read the output block from the output FIFO and put them in temporary buffer
5521 then get CrypOutBuff from temporary buffer*/
5522 for (i = 0U; i < 4U; i++)
5523 {
5524 temp[i] = hcryp->Instance->DOUTR;
5525 }
5526 i = 0U;
5527 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
5528 {
5529 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5530 hcryp->CrypOutCount++;
5531 i++;
5532 }
5533 /*Temporary CrypOutCount Value*/
5534 outcount = hcryp->CrypOutCount;
5535
5536 if ((hcryp->CrypOutCount >= (hcryp->Size / 4U)) && ((outcount * 4U) >= hcryp->Size))
5537 {
5538 /* Disable computation complete flag and errors interrupts */
5539 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
5540
5541 /* Change the CRYP state */
5542 hcryp->State = HAL_CRYP_STATE_READY;
5543
5544 /* Process unlocked */
5545 __HAL_UNLOCK(hcryp);
5546
5547 /* Call output transfer complete callback */
5548#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5549 /*Call registered Output complete callback*/
5550 hcryp->OutCpltCallback(hcryp);
5551#else
5552 /*Call legacy weak Output complete callback*/
5553 HAL_CRYP_OutCpltCallback(hcryp);
5554#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5555 }
5556
5557 else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
5558 {
5559 /* Write the input block in the IN FIFO */
5560 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5561 hcryp->CrypInCount++;
5562 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5563 hcryp->CrypInCount++;
5564 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5565 hcryp->CrypInCount++;
5566 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5567 hcryp->CrypInCount++;
5568 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
5569 {
5570 /* Call Input transfer complete callback */
5571#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5572 /*Call registered Input complete callback*/
5573 hcryp->InCpltCallback(hcryp);
5574#else
5575 /*Call legacy weak Input complete callback*/
5576 HAL_CRYP_InCpltCallback(hcryp);
5577#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5578 }
5579 }
5580 else /* Last block of payload < 128bit*/
5581 {
5582 /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
5583 generated for GCM Encryption & CCM Decryption. Workaround is implemented in polling mode,
5584 so if last block of payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly
5585 generated for GCM Encryption & CCM Decryption. */
5586
5587 /* Compute the number of padding bytes in last block of payload */
5588 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5589
5590 /* Number of valid words (lastwordsize) in last block */
5591 if ((npblb % 4U) == 0U)
5592 {
5593 lastwordsize = (16U - npblb) / 4U;
5594 }
5595 else
5596 {
5597 lastwordsize = ((16U - npblb) / 4U) + 1U;
5598 }
5599
5600 /* Last block optionally pad the data with zeros*/
5601 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
5602 {
5603 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5604 hcryp->CrypInCount++;
5605 }
5606 while (loopcounter < 4U)
5607 {
5608 /* pad the data with zeros to have a complete block */
5609 hcryp->Instance->DINR = 0x0U;
5610 loopcounter++;
5611 }
5612 }
5613#endif /* AES */
5614
5615}
5616
5617
5625static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
5626{
5627 uint32_t loopcounter;
5628 uint32_t size_in_bytes;
5629 uint32_t tmp;
5630 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
5631 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
5632 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
5633 }; /* 8-bit data type */
5634
5635 /***************************** Header phase for GCM/GMAC or CCM *********************************/
5636
5637 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
5638 {
5639 size_in_bytes = hcryp->Init.HeaderSize * 4U;
5640 }
5641 else
5642 {
5643 size_in_bytes = hcryp->Init.HeaderSize;
5644 }
5645
5646 if (size_in_bytes != 0U)
5647 {
5648
5649#if defined(CRYP)
5650
5651 /* Select header phase */
5652 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5653
5654 /* Enable the CRYP peripheral */
5655 __HAL_CRYP_ENABLE(hcryp);
5656
5657 if ((size_in_bytes % 16U) == 0U)
5658 {
5659 /* HeaderSize %4, no padding */
5660 for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
5661 {
5662 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5663 hcryp->CrypHeaderCount++ ;
5664 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5665 hcryp->CrypHeaderCount++ ;
5666 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5667 hcryp->CrypHeaderCount++ ;
5668 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5669 hcryp->CrypHeaderCount++ ;
5670
5671 /* Wait for IFEM to be raised */
5672 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5673 {
5674 /* Disable the CRYP peripheral clock */
5675 __HAL_CRYP_DISABLE(hcryp);
5676
5677 /* Change state */
5678 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5679 hcryp->State = HAL_CRYP_STATE_READY;
5680
5681 /* Process unlocked */
5682 __HAL_UNLOCK(hcryp);
5683 return HAL_ERROR;
5684 }
5685 }
5686 }
5687 else
5688 {
5689 /*Write header block in the IN FIFO without last block */
5690 for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
5691 {
5692 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5693 hcryp->CrypHeaderCount++ ;
5694 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5695 hcryp->CrypHeaderCount++ ;
5696 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5697 hcryp->CrypHeaderCount++ ;
5698 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5699 hcryp->CrypHeaderCount++ ;
5700
5701 /* Wait for IFEM to be raised */
5702 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5703 {
5704 /* Disable the CRYP peripheral clock */
5705 __HAL_CRYP_DISABLE(hcryp);
5706
5707 /* Change state */
5708 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5709 hcryp->State = HAL_CRYP_STATE_READY;
5710
5711 /* Process unlocked */
5712 __HAL_UNLOCK(hcryp);
5713 return HAL_ERROR;
5714 }
5715 }
5716 /* Last block optionally pad the data with zeros*/
5717 for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
5718 {
5719 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5720 hcryp->CrypHeaderCount++ ;
5721 }
5722 /* If the header size is a multiple of words */
5723 if ((size_in_bytes % 4U) == 0U)
5724 {
5725 /* Pad the data with zeros to have a complete block */
5726 while (loopcounter < 4U)
5727 {
5728 hcryp->Instance->DIN = 0x0U;
5729 loopcounter++;
5730 }
5731 }
5732 else
5733 {
5734 /* Enter last bytes, padded with zeroes */
5735 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5736 tmp &= mask[(((hcryp->Init.DataType) >> 5) * 2U) + (size_in_bytes % 4U)];
5737 hcryp->Instance->DIN = tmp;
5738 loopcounter++;
5739 /* Pad the data with zeros to have a complete block */
5740 while (loopcounter < 4U)
5741 {
5742 hcryp->Instance->DIN = 0x0U;
5743 loopcounter++;
5744 }
5745 }
5746 /* Wait for CCF IFEM to be raised */
5747 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5748 {
5749 /* Disable the CRYP peripheral clock */
5750 __HAL_CRYP_DISABLE(hcryp);
5751
5752 /* Change state */
5753 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5754 hcryp->State = HAL_CRYP_STATE_READY;
5755
5756 /* Process unlocked */
5757 __HAL_UNLOCK(hcryp);
5758 return HAL_ERROR;
5759 }
5760 }
5761 /* Wait until the complete message has been processed */
5762 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
5763 {
5764 /* Disable the CRYP peripheral clock */
5765 __HAL_CRYP_DISABLE(hcryp);
5766
5767 /* Change state */
5768 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5769 hcryp->State = HAL_CRYP_STATE_READY;
5770
5771 /* Process unlocked & return error */
5772 __HAL_UNLOCK(hcryp);
5773 return HAL_ERROR;
5774 }
5775
5776#else /* AES */
5777
5778 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5779 {
5780 /* Workaround 1 :only AES before re-enabling the IP, datatype can be configured.*/
5781 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5782
5783 /* Select header phase */
5784 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5785
5786 /* Enable the CRYP peripheral */
5787 __HAL_CRYP_ENABLE(hcryp);
5788
5789 }
5790 /* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */
5791 if ((size_in_bytes % 16U) == 0U)
5792 {
5793 /* No padding */
5794 for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
5795 {
5796 /* Write the input block in the data input register */
5797 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5798 hcryp->CrypHeaderCount++ ;
5799 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5800 hcryp->CrypHeaderCount++ ;
5801 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5802 hcryp->CrypHeaderCount++ ;
5803 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5804 hcryp->CrypHeaderCount++ ;
5805
5806 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5807 {
5808 /* Disable the CRYP peripheral clock */
5809 __HAL_CRYP_DISABLE(hcryp);
5810
5811 /* Change state */
5812 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5813 hcryp->State = HAL_CRYP_STATE_READY;
5814
5815 /* Process unlocked */
5816 __HAL_UNLOCK(hcryp);
5817 return HAL_ERROR;
5818 }
5819 /* Clear CCF flag */
5820 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5821 }
5822 }
5823 else
5824 {
5825 /*Write header block in the IN FIFO without last block */
5826 for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
5827 {
5828 /* Write the input block in the data input register */
5829 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5830 hcryp->CrypHeaderCount++ ;
5831 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5832 hcryp->CrypHeaderCount++ ;
5833 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5834 hcryp->CrypHeaderCount++ ;
5835 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5836 hcryp->CrypHeaderCount++ ;
5837
5838 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5839 {
5840 /* Disable the CRYP peripheral clock */
5841 __HAL_CRYP_DISABLE(hcryp);
5842
5843 /* Change state */
5844 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5845 hcryp->State = HAL_CRYP_STATE_READY;
5846
5847 /* Process unlocked */
5848 __HAL_UNLOCK(hcryp);
5849 return HAL_ERROR;
5850 }
5851 /* Clear CCF flag */
5852 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5853 }
5854 /* Write last complete words */
5855 for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
5856 {
5857 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5858 hcryp->CrypHeaderCount++ ;
5859 }
5860 /* If the header size is a multiple of words */
5861 if ((size_in_bytes % 4U) == 0U)
5862 {
5863 /* Pad the data with zeros to have a complete block */
5864 while (loopcounter < 4U)
5865 {
5866 hcryp->Instance->DINR = 0x0U;
5867 loopcounter++;
5868 }
5869 }
5870 else
5871 {
5872 /* Enter last bytes, padded with zeroes */
5873 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5874 tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
5875 hcryp->Instance->DINR = tmp;
5876 loopcounter++;
5877 /* Pad the data with zeros to have a complete block */
5878 while (loopcounter < 4U)
5879 {
5880 hcryp->Instance->DINR = 0x0U;
5881 loopcounter++;
5882 }
5883 }
5884
5885 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5886 {
5887 /* Disable the CRYP peripheral clock */
5888 __HAL_CRYP_DISABLE(hcryp);
5889
5890 /* Change state */
5891 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5892 hcryp->State = HAL_CRYP_STATE_READY;
5893
5894 /* Process unlocked */
5895 __HAL_UNLOCK(hcryp);
5896 return HAL_ERROR;
5897 }
5898 /* Clear CCF flag */
5899 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5900 }
5901#endif /* End AES or CRYP */
5902 }
5903 else
5904 {
5905#if defined(AES)
5906 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5907 {
5908 /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
5909 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5910
5911 /* Select header phase */
5912 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5913
5914 /* Enable the CRYP peripheral */
5915 __HAL_CRYP_ENABLE(hcryp);
5916 }
5917#endif /* AES */
5918 }
5919 /* Return function status */
5920 return HAL_OK;
5921}
5922
5929static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
5930{
5931 __IO uint32_t count = 0U;
5932 uint32_t loopcounter;
5933 uint32_t headersize_in_bytes;
5934 uint32_t tmp;
5935 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
5936 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
5937 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
5938 }; /* 8-bit data type */
5939
5940 /***************************** Header phase for GCM/GMAC or CCM *********************************/
5941 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
5942 {
5943 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
5944 }
5945 else
5946 {
5947 headersize_in_bytes = hcryp->Init.HeaderSize;
5948 }
5949
5950 if (headersize_in_bytes != 0U)
5951 {
5952
5953#if defined(CRYP)
5954
5955 /* Select header phase */
5956 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5957
5958 /* Enable the CRYP peripheral */
5959 __HAL_CRYP_ENABLE(hcryp);
5960
5961 if ((headersize_in_bytes % 16U) == 0U)
5962 {
5963 /* HeaderSize %4, no padding */
5964 for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
5965 {
5966 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5967 hcryp->CrypHeaderCount++ ;
5968 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5969 hcryp->CrypHeaderCount++ ;
5970 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5971 hcryp->CrypHeaderCount++ ;
5972 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5973 hcryp->CrypHeaderCount++ ;
5974
5975 /* Wait for IFEM to be raised */
5976 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5977 do
5978 {
5979 count-- ;
5980 if (count == 0U)
5981 {
5982 /* Disable the CRYP peripheral clock */
5983 __HAL_CRYP_DISABLE(hcryp);
5984
5985 /* Change state */
5986 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5987 hcryp->State = HAL_CRYP_STATE_READY;
5988
5989 /* Process unlocked */
5990 __HAL_UNLOCK(hcryp);
5991 return HAL_ERROR;
5992 }
5993 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
5994 }
5995 }
5996 else
5997 {
5998 /*Write header block in the IN FIFO without last block */
5999 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
6000 {
6001 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6002 hcryp->CrypHeaderCount++ ;
6003 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6004 hcryp->CrypHeaderCount++ ;
6005 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6006 hcryp->CrypHeaderCount++ ;
6007 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6008 hcryp->CrypHeaderCount++ ;
6009
6010 /* Wait for IFEM to be raised */
6011 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6012 do
6013 {
6014 count-- ;
6015 if (count == 0U)
6016 {
6017 /* Disable the CRYP peripheral clock */
6018 __HAL_CRYP_DISABLE(hcryp);
6019
6020 /* Change state */
6021 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6022 hcryp->State = HAL_CRYP_STATE_READY;
6023
6024 /* Process unlocked */
6025 __HAL_UNLOCK(hcryp);
6026 return HAL_ERROR;
6027 }
6028 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
6029 }
6030 /* Last block optionally pad the data with zeros*/
6031 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
6032 {
6033 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6034 hcryp->CrypHeaderCount++ ;
6035 }
6036 /* If the header size is a multiple of words */
6037 if ((headersize_in_bytes % 4U) == 0U)
6038 {
6039 /* Pad the data with zeros to have a complete block */
6040 while (loopcounter < 4U)
6041 {
6042 hcryp->Instance->DIN = 0x0U;
6043 loopcounter++;
6044 }
6045 }
6046 else
6047 {
6048 /* Enter last bytes, padded with zeroes */
6049 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6050 tmp &= mask[(((hcryp->Init.DataType) >> 5) * 2U) + (headersize_in_bytes % 4U)];
6051 hcryp->Instance->DIN = tmp;
6052 loopcounter++;
6053 /* Pad the data with zeros to have a complete block */
6054 while (loopcounter < 4U)
6055 {
6056 hcryp->Instance->DIN = 0x0U;
6057 loopcounter++;
6058 }
6059 }
6060 /* Wait for IFEM to be raised */
6061 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6062 do
6063 {
6064 count-- ;
6065 if (count == 0U)
6066 {
6067 /* Disable the CRYP peripheral clock */
6068 __HAL_CRYP_DISABLE(hcryp);
6069
6070 /* Change state */
6071 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6072 hcryp->State = HAL_CRYP_STATE_READY;
6073
6074 /* Process unlocked */
6075 __HAL_UNLOCK(hcryp);
6076 return HAL_ERROR;
6077 }
6078 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
6079 }
6080 /* Wait until the complete message has been processed */
6081 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6082 do
6083 {
6084 count-- ;
6085 if (count == 0U)
6086 {
6087 /* Disable the CRYP peripheral clock */
6088 __HAL_CRYP_DISABLE(hcryp);
6089
6090 /* Change state */
6091 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6092 hcryp->State = HAL_CRYP_STATE_READY;
6093
6094 /* Process unlocked */
6095 __HAL_UNLOCK(hcryp);
6096 return HAL_ERROR;
6097 }
6098 } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
6099
6100#else /* AES */
6101
6102 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6103 {
6104 /* Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
6105 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
6106
6107 /* Select header phase */
6108 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
6109
6110 /* Enable the CRYP peripheral */
6111 __HAL_CRYP_ENABLE(hcryp);
6112 }
6113 if ((headersize_in_bytes % 16U) == 0U)
6114 {
6115 /* HeaderSize %4, no padding */
6116 for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
6117 {
6118 /* Write the input block in the data input register */
6119 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6120 hcryp->CrypHeaderCount++ ;
6121 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6122 hcryp->CrypHeaderCount++ ;
6123 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6124 hcryp->CrypHeaderCount++ ;
6125 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6126 hcryp->CrypHeaderCount++ ;
6127
6128 /*Wait on CCF flag*/
6129 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6130 do
6131 {
6132 count-- ;
6133 if (count == 0U)
6134 {
6135 /* Disable the CRYP peripheral clock */
6136 __HAL_CRYP_DISABLE(hcryp);
6137
6138 /* Change state */
6139 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6140 hcryp->State = HAL_CRYP_STATE_READY;
6141
6142 /* Process unlocked */
6143 __HAL_UNLOCK(hcryp);
6144 return HAL_ERROR;
6145 }
6146 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6147
6148 /* Clear CCF flag */
6149 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6150 }
6151 }
6152 else
6153 {
6154 /*Write header block in the IN FIFO without last block */
6155 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
6156 {
6157 /* Write the Input block in the Data Input register */
6158 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6159 hcryp->CrypHeaderCount++ ;
6160 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6161 hcryp->CrypHeaderCount++ ;
6162 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6163 hcryp->CrypHeaderCount++ ;
6164 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6165 hcryp->CrypHeaderCount++ ;
6166
6167 /*Wait on CCF flag*/
6168 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6169 do
6170 {
6171 count-- ;
6172 if (count == 0U)
6173 {
6174 /* Disable the CRYP peripheral clock */
6175 __HAL_CRYP_DISABLE(hcryp);
6176
6177 /* Change state */
6178 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6179 hcryp->State = HAL_CRYP_STATE_READY;
6180
6181 /* Process unlocked */
6182 __HAL_UNLOCK(hcryp);
6183 return HAL_ERROR;
6184 }
6185 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6186
6187 /* Clear CCF flag */
6188 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6189 }
6190 /* Last block optionally pad the data with zeros*/
6191 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
6192 {
6193 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6194 hcryp->CrypHeaderCount++ ;
6195 }
6196 /* If the header size is a multiple of words */
6197 if ((headersize_in_bytes % 4U) == 0U)
6198 {
6199 /* Pad the data with zeros to have a complete block */
6200 while (loopcounter < 4U)
6201 {
6202 hcryp->Instance->DINR = 0x0U;
6203 loopcounter++;
6204 }
6205 }
6206 else
6207 {
6208 /* Enter last bytes, padded with zeroes */
6209 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6210 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6211 hcryp->Instance->DINR = tmp;
6212 loopcounter++;
6213 /* Pad the data with zeros to have a complete block */
6214 while (loopcounter < 4U)
6215 {
6216 hcryp->Instance->DINR = 0x0U;
6217 loopcounter++;
6218 }
6219 }
6220 /*Wait on CCF flag*/
6221 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6222 do
6223 {
6224 count-- ;
6225 if (count == 0U)
6226 {
6227 /* Disable the CRYP peripheral clock */
6228 __HAL_CRYP_DISABLE(hcryp);
6229
6230 /* Change state */
6231 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6232 hcryp->State = HAL_CRYP_STATE_READY;
6233
6234 /* Process unlocked */
6235 __HAL_UNLOCK(hcryp);
6236 return HAL_ERROR;
6237 }
6238 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6239
6240 /* Clear CCF flag */
6241 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6242 }
6243#endif /* End AES or CRYP */
6244 }
6245 else
6246 {
6247#if defined(AES)
6248 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6249 {
6250 /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
6251 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
6252
6253 /* Select header phase */
6254 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
6255
6256 /* Enable the CRYP peripheral */
6257 __HAL_CRYP_ENABLE(hcryp);
6258 }
6259#endif /* AES */
6260 }
6261 /* Return function status */
6262 return HAL_OK;
6263}
6264
6271static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
6272{
6273 uint32_t loopcounter;
6274 uint32_t headersize_in_bytes;
6275#if defined(AES)
6276 uint32_t lastwordsize;
6277 uint32_t npblb;
6278#endif /* AES */
6279 uint32_t tmp;
6280 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
6281 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
6282 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU
6283 }; /* 8-bit data type */
6284
6285 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
6286 {
6287 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
6288 }
6289 else
6290 {
6291 headersize_in_bytes = hcryp->Init.HeaderSize;
6292 }
6293
6294 /***************************** Header phase *********************************/
6295
6296#if defined(CRYP)
6297 if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
6298 {
6299 /* Disable interrupts */
6300 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
6301
6302 /* Disable the CRYP peripheral */
6303 __HAL_CRYP_DISABLE(hcryp);
6304
6305 /* Set the phase */
6306 hcryp->Phase = CRYP_PHASE_PROCESS;
6307
6308 /* Select payload phase once the header phase is performed */
6309 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
6310
6311 /* Enable Interrupts */
6312 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
6313
6314 /* Enable the CRYP peripheral */
6315 __HAL_CRYP_ENABLE(hcryp);
6316 }
6317 else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
6318
6319 {
6320 /* HeaderSize %4, no padding */
6321 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6322 hcryp->CrypHeaderCount++ ;
6323 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6324 hcryp->CrypHeaderCount++ ;
6325 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6326 hcryp->CrypHeaderCount++ ;
6327 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6328 hcryp->CrypHeaderCount++ ;
6329 }
6330 else
6331 {
6332 /* Last block optionally pad the data with zeros*/
6333 for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++)
6334 {
6335 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6336 hcryp->CrypHeaderCount++ ;
6337 }
6338 if ((headersize_in_bytes % 4U) == 0U)
6339 {
6340 /* Pad the data with zeros to have a complete block */
6341 while (loopcounter < 4U)
6342 {
6343 hcryp->Instance->DIN = 0x0U;
6344 loopcounter++;
6345 hcryp->CrypHeaderCount++;
6346 }
6347 }
6348 else
6349 {
6350 /* Enter last bytes, padded with zeros */
6351 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6352 tmp &= mask[(((hcryp->Init.DataType) >> 5) * 2U) + (headersize_in_bytes % 4U)];
6353 hcryp->Instance->DIN = tmp;
6354 loopcounter++;
6355 hcryp->CrypHeaderCount++;
6356 /* Pad the data with zeros to have a complete block */
6357 while (loopcounter < 4U)
6358 {
6359 hcryp->Instance->DIN = 0x0U;
6360 loopcounter++;
6361 hcryp->CrypHeaderCount++;
6362 }
6363 }
6364 }
6365#else /* AES */
6366
6367 if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
6368 {
6369 /* Set the phase */
6370 hcryp->Phase = CRYP_PHASE_PROCESS;
6371
6372 /* Payload phase not supported in CCM AES2 */
6373 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6374 {
6375 /* Select payload phase once the header phase is performed */
6376 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
6377 }
6378 if (hcryp->Init.Algorithm == CRYP_AES_CCM)
6379 {
6380 /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
6381 hcryp->CrypHeaderCount++;
6382 }
6383 /* Write the payload Input block in the IN FIFO */
6384 if (hcryp->Size == 0U)
6385 {
6386 /* Disable interrupts */
6387 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
6388
6389 /* Change the CRYP state */
6390 hcryp->State = HAL_CRYP_STATE_READY;
6391
6392 /* Process unlocked */
6393 __HAL_UNLOCK(hcryp);
6394 }
6395 else if (hcryp->Size >= 16U)
6396 {
6397 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6398 hcryp->CrypInCount++;
6399 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6400 hcryp->CrypInCount++;
6401 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6402 hcryp->CrypInCount++;
6403 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6404 hcryp->CrypInCount++;
6405
6406 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
6407 {
6408 /* Call the input data transfer complete callback */
6409#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6410 /*Call registered Input complete callback*/
6411 hcryp->InCpltCallback(hcryp);
6412#else
6413 /*Call legacy weak Input complete callback*/
6414 HAL_CRYP_InCpltCallback(hcryp);
6415#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6416 }
6417 }
6418 else /* Size < 4 words : first block is the last block*/
6419 {
6420 /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
6421 generated for GCM Encryption. Workaround is implemented in polling mode, so if last block of
6422 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
6423
6424 /* Compute the number of padding bytes in last block of payload */
6425 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
6426
6427 /* Number of valid words (lastwordsize) in last block */
6428 if ((npblb % 4U) == 0U)
6429 {
6430 lastwordsize = (16U - npblb) / 4U;
6431 }
6432 else
6433 {
6434 lastwordsize = ((16U - npblb) / 4U) + 1U;
6435 }
6436
6437 /* Last block optionally pad the data with zeros*/
6438 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
6439 {
6440 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6441 hcryp->CrypInCount++;
6442 }
6443 while (loopcounter < 4U)
6444 {
6445 /* Pad the data with zeros to have a complete block */
6446 hcryp->Instance->DINR = 0x0U;
6447 loopcounter++;
6448 }
6449 }
6450 }
6451 else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
6452 {
6453 /* Write the input block in the IN FIFO */
6454 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6455 hcryp->CrypHeaderCount++;
6456 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6457 hcryp->CrypHeaderCount++;
6458 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6459 hcryp->CrypHeaderCount++;
6460 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6461 hcryp->CrypHeaderCount++;
6462 }
6463 else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
6464 {
6465 /* Last block optionally pad the data with zeros*/
6466 for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++)
6467 {
6468 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6469 hcryp->CrypHeaderCount++ ;
6470 }
6471 /* If the header size is a multiple of words */
6472 if ((headersize_in_bytes % 4U) == 0U)
6473 {
6474 /* Pad the data with zeros to have a complete block */
6475 while (loopcounter < 4U)
6476 {
6477 hcryp->Instance->DINR = 0x0U;
6478 loopcounter++;
6479 hcryp->CrypHeaderCount++;
6480 }
6481 }
6482 else
6483 {
6484 /* Enter last bytes, padded with zeros */
6485 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6486 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6487 hcryp->Instance->DINR = tmp;
6488 loopcounter++;
6489 hcryp->CrypHeaderCount++;
6490 /* Pad the data with zeros to have a complete block */
6491 while (loopcounter < 4U)
6492 {
6493 hcryp->Instance->DINR = 0x0U;
6494 loopcounter++;
6495 hcryp->CrypHeaderCount++;
6496 }
6497 }
6498 }
6499#endif /* End AES or CRYP */
6500}
6501
6502
6510static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6511{
6512 uint32_t lastwordsize;
6513 uint32_t npblb;
6514#if defined(CRYP)
6515 uint32_t iv1temp;
6516 uint32_t temp[4] = {0};
6517 uint32_t temp2[4] = {0};
6518#endif /* CRYP */
6519 uint32_t intermediate_data[4] = {0};
6520 uint32_t index;
6521
6522 /* Compute the number of padding bytes in last block of payload */
6523 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
6524
6525 /* Number of valid words (lastwordsize) in last block */
6526 if ((npblb % 4U) == 0U)
6527 {
6528 lastwordsize = (16U - npblb) / 4U;
6529 }
6530 else
6531 {
6532 lastwordsize = ((16U - npblb) / 4U) + 1U;
6533 }
6534
6535#if defined(CRYP)
6536
6537 /* Workaround 2, case GCM encryption */
6538 if (hcryp->Init.Algorithm == CRYP_AES_GCM)
6539 {
6540 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
6541 {
6542 /*Workaround in order to properly compute authentication tags while doing
6543 a GCM encryption with the last block of payload size inferior to 128 bits*/
6544 /* Disable CRYP to start the final phase */
6545 __HAL_CRYP_DISABLE(hcryp);
6546
6547 /*Update CRYP_IV1R register and ALGOMODE*/
6548 hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R) - 1U);
6549 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
6550
6551 /* Enable CRYP to start the final phase */
6552 __HAL_CRYP_ENABLE(hcryp);
6553 }
6554 /* Last block optionally pad the data with zeros*/
6555 for (index = 0; index < lastwordsize; index ++)
6556 {
6557 /* Write the last input block in the IN FIFO */
6558 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6559 hcryp->CrypInCount++;
6560 }
6561 while (index < 4U)
6562 {
6563 /* Pad the data with zeros to have a complete block */
6564 hcryp->Instance->DIN = 0U;
6565 index++;
6566 }
6567 /* Wait for OFNE flag to be raised */
6568 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6569 {
6570 /* Disable the CRYP peripheral clock */
6571 __HAL_CRYP_DISABLE(hcryp);
6572
6573 /* Change state */
6574 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6575 hcryp->State = HAL_CRYP_STATE_READY;
6576
6577 /* Process Unlocked */
6578 __HAL_UNLOCK(hcryp);
6579#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6580 /*Call registered error callback*/
6581 hcryp->ErrorCallback(hcryp);
6582#else
6583 /*Call legacy weak error callback*/
6584 HAL_CRYP_ErrorCallback(hcryp);
6585#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6586 }
6587 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6588 {
6589 for (index = 0U; index < 4U; index++)
6590 {
6591 /* Read the output block from the output FIFO */
6592 intermediate_data[index] = hcryp->Instance->DOUT;
6593
6594 /* Intermediate data buffer to be used in for the workaround*/
6595 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6596 hcryp->CrypOutCount++;
6597 }
6598 }
6599
6600 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
6601 {
6602 /*workaround in order to properly compute authentication tags while doing
6603 a GCM encryption with the last block of payload size inferior to 128 bits*/
6604 /* Change the AES mode to GCM mode and Select Final phase */
6605 /* configured CHMOD GCM */
6606 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
6607
6608 /* configured final phase */
6609 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
6610
6611 if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B)
6612 {
6613 if ((npblb % 4U) == 1U)
6614 {
6615 intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6616 }
6617 if ((npblb % 4U) == 2U)
6618 {
6619 intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6620 }
6621 if ((npblb % 4U) == 3U)
6622 {
6623 intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6624 }
6625 }
6626 else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B)
6627 {
6628 if ((npblb % 4U) == 1U)
6629 {
6630 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
6631 }
6632 if ((npblb % 4U) == 2U)
6633 {
6634 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
6635 }
6636 if ((npblb % 4U) == 3U)
6637 {
6638 intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
6639 }
6640 }
6641 else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B)
6642 {
6643 if ((npblb % 4U) == 1U)
6644 {
6645 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
6646 }
6647 if ((npblb % 4U) == 2U)
6648 {
6649 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
6650 }
6651 if ((npblb % 4U) == 3U)
6652 {
6653 intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
6654 }
6655 }
6656 else /*CRYP_DATATYPE_1B*/
6657 {
6658 if ((npblb % 4U) == 1U)
6659 {
6660 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
6661 }
6662 if ((npblb % 4U) == 2U)
6663 {
6664 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
6665 }
6666 if ((npblb % 4U) == 3U)
6667 {
6668 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
6669 }
6670 }
6671 for (index = 0U; index < lastwordsize; index ++)
6672 {
6673 /*Write the intermediate_data in the IN FIFO */
6674 hcryp->Instance->DIN = intermediate_data[index];
6675 }
6676 while (index < 4U)
6677 {
6678 /* Pad the data with zeros to have a complete block */
6679 hcryp->Instance->DIN = 0x0U;
6680 index++;
6681 }
6682 /* Wait for OFNE flag to be raised */
6683 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6684 {
6685 /* Disable the CRYP peripheral clock */
6686 __HAL_CRYP_DISABLE(hcryp);
6687
6688 /* Change state */
6689 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6690 hcryp->State = HAL_CRYP_STATE_READY;
6691
6692 /* Process unlocked */
6693 __HAL_UNLOCK(hcryp);
6694#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6695 /*Call registered error callback*/
6696 hcryp->ErrorCallback(hcryp);
6697#else
6698 /*Call legacy weak error callback*/
6699 HAL_CRYP_ErrorCallback(hcryp);
6700#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6701 }
6702
6703 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6704 {
6705 for (index = 0U; index < 4U; index++)
6706 {
6707 intermediate_data[index] = hcryp->Instance->DOUT;
6708 }
6709 }
6710 }
6711 } /* End of GCM encryption */
6712 else
6713 {
6714 /* Workaround 2, case CCM decryption, in order to properly compute
6715 authentication tags while doing a CCM decryption with the last block
6716 of payload size inferior to 128 bits*/
6717
6718 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
6719 {
6720 iv1temp = hcryp->Instance->CSGCMCCM7R;
6721
6722 /* Disable CRYP to start the final phase */
6723 __HAL_CRYP_DISABLE(hcryp);
6724
6725 temp[0] = hcryp->Instance->CSGCMCCM0R;
6726 temp[1] = hcryp->Instance->CSGCMCCM1R;
6727 temp[2] = hcryp->Instance->CSGCMCCM2R;
6728 temp[3] = hcryp->Instance->CSGCMCCM3R;
6729
6730 hcryp->Instance->IV1RR = iv1temp;
6731
6732 /* Configured CHMOD CTR */
6733 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
6734
6735 /* Enable CRYP to start the final phase */
6736 __HAL_CRYP_ENABLE(hcryp);
6737 }
6738 /* Last block optionally pad the data with zeros*/
6739 for (index = 0; index < lastwordsize; index ++)
6740 {
6741 /* Write the last Input block in the IN FIFO */
6742 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6743 hcryp->CrypInCount++;
6744 }
6745 while (index < 4U)
6746 {
6747 /* Pad the data with zeros to have a complete block */
6748 hcryp->Instance->DIN = 0U;
6749 index++;
6750 }
6751 /* Wait for OFNE flag to be raised */
6752 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6753 {
6754 /* Disable the CRYP peripheral clock */
6755 __HAL_CRYP_DISABLE(hcryp);
6756
6757 /* Change state */
6758 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6759 hcryp->State = HAL_CRYP_STATE_READY;
6760
6761 /* Process Unlocked */
6762 __HAL_UNLOCK(hcryp);
6763#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6764 /*Call registered error callback*/
6765 hcryp->ErrorCallback(hcryp);
6766#else
6767 /*Call legacy weak error callback*/
6768 HAL_CRYP_ErrorCallback(hcryp);
6769#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6770 }
6771
6772 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6773 {
6774 for (index = 0U; index < 4U; index++)
6775 {
6776 /* Read the Output block from the Output FIFO */
6777 intermediate_data[index] = hcryp->Instance->DOUT;
6778
6779 /*intermediate data buffer to be used in for the workaround*/
6780 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6781 hcryp->CrypOutCount++;
6782 }
6783 }
6784
6785 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
6786 {
6787 temp2[0] = hcryp->Instance->CSGCMCCM0R;
6788 temp2[1] = hcryp->Instance->CSGCMCCM1R;
6789 temp2[2] = hcryp->Instance->CSGCMCCM2R;
6790 temp2[3] = hcryp->Instance->CSGCMCCM3R;
6791
6792 /* configured CHMOD CCM */
6793 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
6794
6795 /* configured Header phase */
6796 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
6797
6798 /*set to zero the bits corresponding to the padded bits*/
6799 for (index = lastwordsize; index < 4U; index ++)
6800 {
6801 intermediate_data[index] = 0U;
6802 }
6803 if ((npblb % 4U) == 1U)
6804 {
6805 intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6806 }
6807 if ((npblb % 4U) == 2U)
6808 {
6809 intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6810 }
6811 if ((npblb % 4U) == 3U)
6812 {
6813 intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6814 }
6815 for (index = 0U; index < 4U ; index ++)
6816 {
6817 intermediate_data[index] ^= temp[index];
6818 intermediate_data[index] ^= temp2[index];
6819 }
6820 for (index = 0U; index < 4U; index ++)
6821 {
6822 /* Write the last Input block in the IN FIFO */
6823 hcryp->Instance->DIN = intermediate_data[index] ;
6824 }
6825
6826 /* Wait for BUSY flag to be raised */
6827 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
6828 {
6829 /* Disable the CRYP peripheral clock */
6830 __HAL_CRYP_DISABLE(hcryp);
6831
6832 /* Change state */
6833 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6834 hcryp->State = HAL_CRYP_STATE_READY;
6835
6836 /* Process Unlocked */
6837 __HAL_UNLOCK(hcryp);
6838#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6839 /*Call registered error callback*/
6840 hcryp->ErrorCallback(hcryp);
6841#else
6842 /*Call legacy weak error callback*/
6843 HAL_CRYP_ErrorCallback(hcryp);
6844#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6845 }
6846 }
6847 } /* End of CCM WKA*/
6848
6849 /* Process Unlocked */
6850 __HAL_UNLOCK(hcryp);
6851
6852#else /* AES */
6853
6854 /*Workaround 2: case GCM encryption, during payload phase and before inserting
6855 the last block of paylaod, which size is inferior to 128 bits */
6856
6857 if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
6858 {
6859 /* configured CHMOD CTR */
6860 MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR);
6861 }
6862 /* last block optionally pad the data with zeros*/
6863 for (index = 0U; index < lastwordsize; index ++)
6864 {
6865 /* Write the last Input block in the IN FIFO */
6866 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6867 hcryp->CrypInCount++;
6868 }
6869 while (index < 4U)
6870 {
6871 /* pad the data with zeros to have a complete block */
6872 hcryp->Instance->DINR = 0U;
6873 index++;
6874 }
6875 /* Wait for CCF flag to be raised */
6876 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
6877 {
6878 hcryp->State = HAL_CRYP_STATE_READY;
6879 __HAL_UNLOCK(hcryp);
6880#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6881 /*Call registered error callback*/
6882 hcryp->ErrorCallback(hcryp);
6883#else
6884 /*Call legacy weak error callback*/
6885 HAL_CRYP_ErrorCallback(hcryp);
6886#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6887 }
6888
6889 /* Clear CCF Flag */
6890 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6891
6892 for (index = 0U; index < 4U; index++)
6893 {
6894 /* Read the Output block from the Output FIFO */
6895 intermediate_data[index] = hcryp->Instance->DOUTR;
6896
6897 /*intermediate data buffer to be used in the workaround*/
6898 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6899 hcryp->CrypOutCount++;
6900 }
6901
6902 if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
6903 {
6904 /* configured CHMOD GCM */
6905 MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_GCM_GMAC);
6906
6907 /* Select final phase */
6908 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
6909
6910 if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_32B)
6911 {
6912 if ((npblb % 4U) == 1U)
6913 {
6914 intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6915 }
6916 if ((npblb % 4U) == 2U)
6917 {
6918 intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6919 }
6920 if ((npblb % 4U) == 3U)
6921 {
6922 intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6923 }
6924 }
6925 else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_8B)
6926 {
6927 if ((npblb % 4U) == 1U)
6928 {
6929 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
6930 }
6931 if ((npblb % 4U) == 2U)
6932 {
6933 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
6934 }
6935 if ((npblb % 4U) == 3U)
6936 {
6937 intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
6938 }
6939 }
6940 else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_16B)
6941 {
6942 if ((npblb % 4U) == 1U)
6943 {
6944 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
6945 }
6946 if ((npblb % 4U) == 2U)
6947 {
6948 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
6949 }
6950 if ((npblb % 4U) == 3U)
6951 {
6952 intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
6953 }
6954 }
6955 else /*CRYP_DATATYPE_1B*/
6956 {
6957 if ((npblb % 4U) == 1U)
6958 {
6959 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
6960 }
6961 if ((npblb % 4U) == 2U)
6962 {
6963 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
6964 }
6965 if ((npblb % 4U) == 3U)
6966 {
6967 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
6968 }
6969 }
6970
6971 /*Write the intermediate_data in the IN FIFO */
6972 for (index = 0U; index < lastwordsize; index ++)
6973 {
6974 hcryp->Instance->DINR = intermediate_data[index];
6975 }
6976 while (index < 4U)
6977 {
6978 /* pad the data with zeros to have a complete block */
6979 hcryp->Instance->DINR = 0U;
6980 index++;
6981 }
6982 /* Wait for CCF flag to be raised */
6983 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
6984 {
6985 /* Disable the CRYP peripheral clock */
6986 __HAL_CRYP_DISABLE(hcryp);
6987
6988 /* Change state */
6989 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6990 hcryp->State = HAL_CRYP_STATE_READY;
6991
6992 /* Process Unlocked */
6993 __HAL_UNLOCK(hcryp);
6994#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6995 /*Call registered error callback*/
6996 hcryp->ErrorCallback(hcryp);
6997#else
6998 /*Call legacy weak error callback*/
6999 HAL_CRYP_ErrorCallback(hcryp);
7000#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
7001 }
7002 /* Clear CCF Flag */
7003 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
7004
7005 for (index = 0U; index < 4U; index++)
7006 {
7007 intermediate_data[index] = hcryp->Instance->DOUTR;
7008 }
7009 }/*End of Workaround 2*/
7010#endif /* End AES or CRYP */
7011}
7012#endif /* AES or GCM CCM defined*/
7013#if defined (CRYP)
7014#if defined (CRYP_CR_ALGOMODE_AES_GCM)
7022static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7023{
7024 uint32_t tickstart;
7025
7026 /* Get timeout */
7027 tickstart = HAL_GetTick();
7028
7029 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
7030 {
7031 /* Check for the Timeout */
7032 if (Timeout != HAL_MAX_DELAY)
7033 {
7034 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7035 {
7036 return HAL_ERROR;
7037 }
7038 }
7039 }
7040 return HAL_OK;
7041}
7042#endif /* GCM CCM defined*/
7050static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7051{
7052 uint32_t tickstart;
7053
7054 /* Get timeout */
7055 tickstart = HAL_GetTick();
7056
7057 while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
7058 {
7059 /* Check for the Timeout */
7060 if (Timeout != HAL_MAX_DELAY)
7061 {
7062 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7063 {
7064 return HAL_ERROR;
7065 }
7066 }
7067 }
7068 return HAL_OK;
7069}
7070
7071
7079static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7080{
7081 uint32_t tickstart;
7082
7083 /* Get timeout */
7084 tickstart = HAL_GetTick();
7085
7086 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
7087 {
7088 /* Check for the Timeout */
7089 if (Timeout != HAL_MAX_DELAY)
7090 {
7091 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7092 {
7093 return HAL_ERROR;
7094 }
7095 }
7096 }
7097 return HAL_OK;
7098}
7099
7100#else /* AES */
7101
7109static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7110{
7111 uint32_t tickstart;
7112
7113 /* Get timeout */
7114 tickstart = HAL_GetTick();
7115
7116 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
7117 {
7118 /* Check for the Timeout */
7119 if (Timeout != HAL_MAX_DELAY)
7120 {
7121 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7122 {
7123 return HAL_ERROR;
7124 }
7125 }
7126 }
7127 return HAL_OK;
7128}
7129
7130#endif /* End AES or CRYP */
7131
7132
7136
7140
7144
7145#endif /* HAL_CRYP_MODULE_ENABLED */
7146
7147
7151#endif /* TinyAES or CRYP*/
7155
HAL_DMA_Start_IT
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
DMA_HandleTypeDef
struct __DMA_HandleTypeDef DMA_HandleTypeDef
DMA handle Structure definition.
HAL_GetTick
uint32_t HAL_GetTick(void)
Provides a tick value in millisecond.
Definition stm32f4xx_hal.c:323
assert_param
#define assert_param(expr)
Definition stm32_assert_template.h:46
stm32f4xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
HAL_IS_BIT_SET
#define HAL_IS_BIT_SET(REG, BIT)
Definition stm32f4xx_hal_def.h:63
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition stm32f4xx_hal_def.h:39
HAL_ERROR
@ HAL_ERROR
Definition stm32f4xx_hal_def.h:41
HAL_OK
@ HAL_OK
Definition stm32f4xx_hal_def.h:40
__HAL_UNLOCK
#define __HAL_UNLOCK(__HANDLE__)
Definition stm32f4xx_hal_def.h:105
HAL_IS_BIT_CLR
#define HAL_IS_BIT_CLR(REG, BIT)
Definition stm32f4xx_hal_def.h:64
HAL_MAX_DELAY
#define HAL_MAX_DELAY
Definition stm32f4xx_hal_def.h:61
HAL_UNLOCKED
@ HAL_UNLOCKED
Definition stm32f4xx_hal_def.h:51
__HAL_LOCK
#define __HAL_LOCK(__HANDLE__)
Definition stm32f4xx_hal_def.h:93