STM32F4xx HAL Driver master
STM32CubeF4 HAL / LL Drivers API Reference
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stm32f4xx_hal_can.c
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1
211
212/* Includes ------------------------------------------------------------------*/
213#include "stm32f4xx_hal.h"
214
218
219#if defined(CAN1)
220
225
226#ifdef HAL_CAN_MODULE_ENABLED
227
228#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
229#error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once"
230#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
231
232/* Private typedef -----------------------------------------------------------*/
233/* Private define ------------------------------------------------------------*/
237#define CAN_TIMEOUT_VALUE 10U
238#define CAN_WAKEUP_TIMEOUT_COUNTER 1000000U
242/* Private macro -------------------------------------------------------------*/
243/* Private variables ---------------------------------------------------------*/
244/* Private function prototypes -----------------------------------------------*/
245/* Exported functions --------------------------------------------------------*/
246
250
267
275HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
276{
277 uint32_t tickstart;
278
279 /* Check CAN handle */
280 if (hcan == NULL)
281 {
282 return HAL_ERROR;
283 }
284
285 /* Check the parameters */
286 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
287 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode));
288 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff));
289 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp));
290 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission));
291 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked));
292 assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority));
293 assert_param(IS_CAN_MODE(hcan->Init.Mode));
294 assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth));
295 assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1));
296 assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));
297 assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
298
299#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
300 if (hcan->State == HAL_CAN_STATE_RESET)
301 {
302 /* Reset callbacks to legacy functions */
303 hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback; /* Legacy weak RxFifo0MsgPendingCallback */
304 hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback; /* Legacy weak RxFifo0FullCallback */
305 hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback; /* Legacy weak RxFifo1MsgPendingCallback */
306 hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback; /* Legacy weak RxFifo1FullCallback */
307 hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback; /* Legacy weak TxMailbox0CompleteCallback */
308 hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback; /* Legacy weak TxMailbox1CompleteCallback */
309 hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback; /* Legacy weak TxMailbox2CompleteCallback */
310 hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback; /* Legacy weak TxMailbox0AbortCallback */
311 hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback; /* Legacy weak TxMailbox1AbortCallback */
312 hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback; /* Legacy weak TxMailbox2AbortCallback */
313 hcan->SleepCallback = HAL_CAN_SleepCallback; /* Legacy weak SleepCallback */
314 hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback; /* Legacy weak WakeUpFromRxMsgCallback */
315 hcan->ErrorCallback = HAL_CAN_ErrorCallback; /* Legacy weak ErrorCallback */
316
317 if (hcan->MspInitCallback == NULL)
318 {
319 hcan->MspInitCallback = HAL_CAN_MspInit; /* Legacy weak MspInit */
320 }
321
322 /* Init the low level hardware: CLOCK, NVIC */
323 hcan->MspInitCallback(hcan);
324 }
325
326#else
327 if (hcan->State == HAL_CAN_STATE_RESET)
328 {
329 /* Init the low level hardware: CLOCK, NVIC */
330 HAL_CAN_MspInit(hcan);
331 }
332#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
333
334 /* Request initialisation */
335 SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
336
337 /* Get tick */
338 tickstart = HAL_GetTick();
339
340 /* Wait initialisation acknowledge */
341 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
342 {
343 if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
344 {
345 /* Update error code */
346 hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
347
348 /* Change CAN state */
349 hcan->State = HAL_CAN_STATE_ERROR;
350
351 return HAL_ERROR;
352 }
353 }
354
355 /* Exit from sleep mode */
356 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
357
358 /* Get tick */
359 tickstart = HAL_GetTick();
360
361 /* Check Sleep mode leave acknowledge */
362 while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
363 {
364 if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
365 {
366 /* Update error code */
367 hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
368
369 /* Change CAN state */
370 hcan->State = HAL_CAN_STATE_ERROR;
371
372 return HAL_ERROR;
373 }
374 }
375
376 /* Set the time triggered communication mode */
377 if (hcan->Init.TimeTriggeredMode == ENABLE)
378 {
379 SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
380 }
381 else
382 {
383 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
384 }
385
386 /* Set the automatic bus-off management */
387 if (hcan->Init.AutoBusOff == ENABLE)
388 {
389 SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
390 }
391 else
392 {
393 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
394 }
395
396 /* Set the automatic wake-up mode */
397 if (hcan->Init.AutoWakeUp == ENABLE)
398 {
399 SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
400 }
401 else
402 {
403 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
404 }
405
406 /* Set the automatic retransmission */
407 if (hcan->Init.AutoRetransmission == ENABLE)
408 {
409 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
410 }
411 else
412 {
413 SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
414 }
415
416 /* Set the receive FIFO locked mode */
417 if (hcan->Init.ReceiveFifoLocked == ENABLE)
418 {
419 SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
420 }
421 else
422 {
423 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
424 }
425
426 /* Set the transmit FIFO priority */
427 if (hcan->Init.TransmitFifoPriority == ENABLE)
428 {
429 SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
430 }
431 else
432 {
433 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
434 }
435
436 /* Set the bit timing register */
437 WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
438 hcan->Init.SyncJumpWidth |
439 hcan->Init.TimeSeg1 |
440 hcan->Init.TimeSeg2 |
441 (hcan->Init.Prescaler - 1U)));
442
443 /* Initialize the error code */
444 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
445
446 /* Initialize the CAN state */
447 hcan->State = HAL_CAN_STATE_READY;
448
449 /* Return function status */
450 return HAL_OK;
451}
452
460HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
461{
462 /* Check CAN handle */
463 if (hcan == NULL)
464 {
465 return HAL_ERROR;
466 }
467
468 /* Check the parameters */
469 assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
470
471 /* Stop the CAN module */
472 (void)HAL_CAN_Stop(hcan);
473
474#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
475 if (hcan->MspDeInitCallback == NULL)
476 {
477 hcan->MspDeInitCallback = HAL_CAN_MspDeInit; /* Legacy weak MspDeInit */
478 }
479
480 /* DeInit the low level hardware: CLOCK, NVIC */
481 hcan->MspDeInitCallback(hcan);
482
483#else
484 /* DeInit the low level hardware: CLOCK, NVIC */
485 HAL_CAN_MspDeInit(hcan);
486#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
487
488 /* Reset the CAN peripheral */
489 SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
490
491 /* Reset the CAN ErrorCode */
492 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
493
494 /* Change CAN state */
495 hcan->State = HAL_CAN_STATE_RESET;
496
497 /* Return function status */
498 return HAL_OK;
499}
500
507__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan)
508{
509 /* Prevent unused argument(s) compilation warning */
510 UNUSED(hcan);
511
512 /* NOTE : This function Should not be modified, when the callback is needed,
513 the HAL_CAN_MspInit could be implemented in the user file
514 */
515}
516
523__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
524{
525 /* Prevent unused argument(s) compilation warning */
526 UNUSED(hcan);
527
528 /* NOTE : This function Should not be modified, when the callback is needed,
529 the HAL_CAN_MspDeInit could be implemented in the user file
530 */
531}
532
533#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
559HAL_StatusTypeDef HAL_CAN_RegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID,
560 void (* pCallback)(CAN_HandleTypeDef *_hcan))
561{
562 HAL_StatusTypeDef status = HAL_OK;
563
564 if (pCallback == NULL)
565 {
566 /* Update the error code */
567 hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
568
569 return HAL_ERROR;
570 }
571
572 if (hcan->State == HAL_CAN_STATE_READY)
573 {
574 switch (CallbackID)
575 {
576 case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :
577 hcan->TxMailbox0CompleteCallback = pCallback;
578 break;
579
580 case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :
581 hcan->TxMailbox1CompleteCallback = pCallback;
582 break;
583
584 case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :
585 hcan->TxMailbox2CompleteCallback = pCallback;
586 break;
587
588 case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :
589 hcan->TxMailbox0AbortCallback = pCallback;
590 break;
591
592 case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :
593 hcan->TxMailbox1AbortCallback = pCallback;
594 break;
595
596 case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :
597 hcan->TxMailbox2AbortCallback = pCallback;
598 break;
599
600 case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :
601 hcan->RxFifo0MsgPendingCallback = pCallback;
602 break;
603
604 case HAL_CAN_RX_FIFO0_FULL_CB_ID :
605 hcan->RxFifo0FullCallback = pCallback;
606 break;
607
608 case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :
609 hcan->RxFifo1MsgPendingCallback = pCallback;
610 break;
611
612 case HAL_CAN_RX_FIFO1_FULL_CB_ID :
613 hcan->RxFifo1FullCallback = pCallback;
614 break;
615
616 case HAL_CAN_SLEEP_CB_ID :
617 hcan->SleepCallback = pCallback;
618 break;
619
620 case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :
621 hcan->WakeUpFromRxMsgCallback = pCallback;
622 break;
623
624 case HAL_CAN_ERROR_CB_ID :
625 hcan->ErrorCallback = pCallback;
626 break;
627
628 case HAL_CAN_MSPINIT_CB_ID :
629 hcan->MspInitCallback = pCallback;
630 break;
631
632 case HAL_CAN_MSPDEINIT_CB_ID :
633 hcan->MspDeInitCallback = pCallback;
634 break;
635
636 default :
637 /* Update the error code */
638 hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
639
640 /* Return error status */
641 status = HAL_ERROR;
642 break;
643 }
644 }
645 else if (hcan->State == HAL_CAN_STATE_RESET)
646 {
647 switch (CallbackID)
648 {
649 case HAL_CAN_MSPINIT_CB_ID :
650 hcan->MspInitCallback = pCallback;
651 break;
652
653 case HAL_CAN_MSPDEINIT_CB_ID :
654 hcan->MspDeInitCallback = pCallback;
655 break;
656
657 default :
658 /* Update the error code */
659 hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
660
661 /* Return error status */
662 status = HAL_ERROR;
663 break;
664 }
665 }
666 else
667 {
668 /* Update the error code */
669 hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
670
671 /* Return error status */
672 status = HAL_ERROR;
673 }
674
675 return status;
676}
677
702HAL_StatusTypeDef HAL_CAN_UnRegisterCallback(CAN_HandleTypeDef *hcan, HAL_CAN_CallbackIDTypeDef CallbackID)
703{
704 HAL_StatusTypeDef status = HAL_OK;
705
706 if (hcan->State == HAL_CAN_STATE_READY)
707 {
708 switch (CallbackID)
709 {
710 case HAL_CAN_TX_MAILBOX0_COMPLETE_CB_ID :
711 hcan->TxMailbox0CompleteCallback = HAL_CAN_TxMailbox0CompleteCallback;
712 break;
713
714 case HAL_CAN_TX_MAILBOX1_COMPLETE_CB_ID :
715 hcan->TxMailbox1CompleteCallback = HAL_CAN_TxMailbox1CompleteCallback;
716 break;
717
718 case HAL_CAN_TX_MAILBOX2_COMPLETE_CB_ID :
719 hcan->TxMailbox2CompleteCallback = HAL_CAN_TxMailbox2CompleteCallback;
720 break;
721
722 case HAL_CAN_TX_MAILBOX0_ABORT_CB_ID :
723 hcan->TxMailbox0AbortCallback = HAL_CAN_TxMailbox0AbortCallback;
724 break;
725
726 case HAL_CAN_TX_MAILBOX1_ABORT_CB_ID :
727 hcan->TxMailbox1AbortCallback = HAL_CAN_TxMailbox1AbortCallback;
728 break;
729
730 case HAL_CAN_TX_MAILBOX2_ABORT_CB_ID :
731 hcan->TxMailbox2AbortCallback = HAL_CAN_TxMailbox2AbortCallback;
732 break;
733
734 case HAL_CAN_RX_FIFO0_MSG_PENDING_CB_ID :
735 hcan->RxFifo0MsgPendingCallback = HAL_CAN_RxFifo0MsgPendingCallback;
736 break;
737
738 case HAL_CAN_RX_FIFO0_FULL_CB_ID :
739 hcan->RxFifo0FullCallback = HAL_CAN_RxFifo0FullCallback;
740 break;
741
742 case HAL_CAN_RX_FIFO1_MSG_PENDING_CB_ID :
743 hcan->RxFifo1MsgPendingCallback = HAL_CAN_RxFifo1MsgPendingCallback;
744 break;
745
746 case HAL_CAN_RX_FIFO1_FULL_CB_ID :
747 hcan->RxFifo1FullCallback = HAL_CAN_RxFifo1FullCallback;
748 break;
749
750 case HAL_CAN_SLEEP_CB_ID :
751 hcan->SleepCallback = HAL_CAN_SleepCallback;
752 break;
753
754 case HAL_CAN_WAKEUP_FROM_RX_MSG_CB_ID :
755 hcan->WakeUpFromRxMsgCallback = HAL_CAN_WakeUpFromRxMsgCallback;
756 break;
757
758 case HAL_CAN_ERROR_CB_ID :
759 hcan->ErrorCallback = HAL_CAN_ErrorCallback;
760 break;
761
762 case HAL_CAN_MSPINIT_CB_ID :
763 hcan->MspInitCallback = HAL_CAN_MspInit;
764 break;
765
766 case HAL_CAN_MSPDEINIT_CB_ID :
767 hcan->MspDeInitCallback = HAL_CAN_MspDeInit;
768 break;
769
770 default :
771 /* Update the error code */
772 hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
773
774 /* Return error status */
775 status = HAL_ERROR;
776 break;
777 }
778 }
779 else if (hcan->State == HAL_CAN_STATE_RESET)
780 {
781 switch (CallbackID)
782 {
783 case HAL_CAN_MSPINIT_CB_ID :
784 hcan->MspInitCallback = HAL_CAN_MspInit;
785 break;
786
787 case HAL_CAN_MSPDEINIT_CB_ID :
788 hcan->MspDeInitCallback = HAL_CAN_MspDeInit;
789 break;
790
791 default :
792 /* Update the error code */
793 hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
794
795 /* Return error status */
796 status = HAL_ERROR;
797 break;
798 }
799 }
800 else
801 {
802 /* Update the error code */
803 hcan->ErrorCode |= HAL_CAN_ERROR_INVALID_CALLBACK;
804
805 /* Return error status */
806 status = HAL_ERROR;
807 }
808
809 return status;
810}
811#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
812
816
830
840HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, const CAN_FilterTypeDef *sFilterConfig)
841{
842 uint32_t filternbrbitpos;
843 CAN_TypeDef *can_ip;
844 HAL_CAN_StateTypeDef state = hcan->State;
845
846 if ((state == HAL_CAN_STATE_READY) ||
847 (state == HAL_CAN_STATE_LISTENING))
848 {
849 /* Check the parameters */
850 assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh));
851 assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow));
852 assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh));
853 assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow));
854 assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
855 assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
856 assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
857 assert_param(IS_CAN_FILTER_ACTIVATION(sFilterConfig->FilterActivation));
858
859#if defined(CAN3)
860 /* Check the CAN instance */
861 if (hcan->Instance == CAN3)
862 {
863 /* CAN3 is single instance with 14 dedicated filters banks */
864 can_ip = hcan->Instance;
865
866 /* Check the parameters */
867 assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
868 }
869 else
870 {
871 /* CAN1 and CAN2 are dual instances with 28 common filters banks */
872 /* Select master instance to access the filter banks */
873 can_ip = CAN1;
874
875 /* Check the parameters */
876 assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));
877 assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
878 }
879#elif defined(CAN2)
880 /* CAN1 and CAN2 are dual instances with 28 common filters banks */
881 /* Select master instance to access the filter banks */
882 can_ip = CAN1;
883
884 /* Check the parameters */
885 assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));
886 assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
887#else
888 /* CAN1 is single instance with 14 dedicated filters banks */
889 can_ip = hcan->Instance;
890
891 /* Check the parameters */
892 assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
893#endif /* CAN3 */
894
895 /* Initialisation mode for the filter */
896 SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
897
898#if defined(CAN3)
899 /* Check the CAN instance */
900 if (can_ip == CAN1)
901 {
902 /* Select the start filter number of CAN2 slave instance */
903 CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
904 SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
905 }
906
907#elif defined(CAN2)
908 /* Select the start filter number of CAN2 slave instance */
909 CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
910 SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
911
912#endif /* CAN3 */
913 /* Convert filter number into bit position */
914 filternbrbitpos = (uint32_t)1 << (sFilterConfig->FilterBank & 0x1FU);
915
916 /* Filter Deactivation */
917 CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
918
919 /* Filter Scale */
920 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
921 {
922 /* 16-bit scale for the filter */
923 CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
924
925 /* First 16-bit identifier and First 16-bit mask */
926 /* Or First 16-bit identifier and Second 16-bit identifier */
927 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
928 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
929 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
930
931 /* Second 16-bit identifier and Second 16-bit mask */
932 /* Or Third 16-bit identifier and Fourth 16-bit identifier */
933 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
934 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
935 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
936 }
937
938 if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
939 {
940 /* 32-bit scale for the filter */
941 SET_BIT(can_ip->FS1R, filternbrbitpos);
942
943 /* 32-bit identifier or First 32-bit identifier */
944 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
945 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
946 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
947
948 /* 32-bit mask or Second 32-bit identifier */
949 can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
950 ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
951 (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
952 }
953
954 /* Filter Mode */
955 if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
956 {
957 /* Id/Mask mode for the filter*/
958 CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
959 }
960 else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
961 {
962 /* Identifier list mode for the filter*/
963 SET_BIT(can_ip->FM1R, filternbrbitpos);
964 }
965
966 /* Filter FIFO assignment */
967 if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
968 {
969 /* FIFO 0 assignation for the filter */
970 CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
971 }
972 else
973 {
974 /* FIFO 1 assignation for the filter */
975 SET_BIT(can_ip->FFA1R, filternbrbitpos);
976 }
977
978 /* Filter activation */
979 if (sFilterConfig->FilterActivation == CAN_FILTER_ENABLE)
980 {
981 SET_BIT(can_ip->FA1R, filternbrbitpos);
982 }
983
984 /* Leave the initialisation mode for the filter */
985 CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
986
987 /* Return function status */
988 return HAL_OK;
989 }
990 else
991 {
992 /* Update error code */
993 hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
994
995 return HAL_ERROR;
996 }
997}
998
1002
1029
1036HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
1037{
1038 uint32_t tickstart;
1039
1040 if (hcan->State == HAL_CAN_STATE_READY)
1041 {
1042 /* Change CAN peripheral state */
1043 hcan->State = HAL_CAN_STATE_LISTENING;
1044
1045 /* Request leave initialisation */
1046 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
1047
1048 /* Get tick */
1049 tickstart = HAL_GetTick();
1050
1051 /* Wait the acknowledge */
1052 while ((hcan->Instance->MSR & CAN_MSR_INAK) != 0U)
1053 {
1054 /* Check for the Timeout */
1055 if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
1056 {
1057 /* Update error code */
1058 hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
1059
1060 /* Change CAN state */
1061 hcan->State = HAL_CAN_STATE_ERROR;
1062
1063 return HAL_ERROR;
1064 }
1065 }
1066
1067 /* Reset the CAN ErrorCode */
1068 hcan->ErrorCode = HAL_CAN_ERROR_NONE;
1069
1070 /* Return function status */
1071 return HAL_OK;
1072 }
1073 else
1074 {
1075 /* Update error code */
1076 hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
1077
1078 return HAL_ERROR;
1079 }
1080}
1081
1088HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
1089{
1090 uint32_t tickstart;
1091
1092 if (hcan->State == HAL_CAN_STATE_LISTENING)
1093 {
1094 /* Request initialisation */
1095 SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
1096
1097 /* Get tick */
1098 tickstart = HAL_GetTick();
1099
1100 /* Wait the acknowledge */
1101 while ((hcan->Instance->MSR & CAN_MSR_INAK) == 0U)
1102 {
1103 /* Check for the Timeout */
1104 if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
1105 {
1106 /* Update error code */
1107 hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
1108
1109 /* Change CAN state */
1110 hcan->State = HAL_CAN_STATE_ERROR;
1111
1112 return HAL_ERROR;
1113 }
1114 }
1115
1116 /* Exit from sleep mode */
1117 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
1118
1119 /* Change CAN peripheral state */
1120 hcan->State = HAL_CAN_STATE_READY;
1121
1122 /* Return function status */
1123 return HAL_OK;
1124 }
1125 else
1126 {
1127 /* Update error code */
1128 hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED;
1129
1130 return HAL_ERROR;
1131 }
1132}
1133
1143HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
1144{
1145 HAL_CAN_StateTypeDef state = hcan->State;
1146
1147 if ((state == HAL_CAN_STATE_READY) ||
1148 (state == HAL_CAN_STATE_LISTENING))
1149 {
1150 /* Request Sleep mode */
1151 SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
1152
1153 /* Return function status */
1154 return HAL_OK;
1155 }
1156 else
1157 {
1158 /* Update error code */
1159 hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
1160
1161 /* Return function status */
1162 return HAL_ERROR;
1163 }
1164}
1165
1174HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
1175{
1176 __IO uint32_t count = 0;
1177 HAL_CAN_StateTypeDef state = hcan->State;
1178
1179 if ((state == HAL_CAN_STATE_READY) ||
1180 (state == HAL_CAN_STATE_LISTENING))
1181 {
1182 /* Wake up request */
1183 CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
1184
1185 /* Wait sleep mode is exited */
1186 do
1187 {
1188 /* Increment counter */
1189 count++;
1190
1191 /* Check if timeout is reached */
1192 if (count > CAN_WAKEUP_TIMEOUT_COUNTER)
1193 {
1194 /* Update error code */
1195 hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
1196
1197 return HAL_ERROR;
1198 }
1199 } while ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U);
1200
1201 /* Return function status */
1202 return HAL_OK;
1203 }
1204 else
1205 {
1206 /* Update error code */
1207 hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
1208
1209 return HAL_ERROR;
1210 }
1211}
1212
1221uint32_t HAL_CAN_IsSleepActive(const CAN_HandleTypeDef *hcan)
1222{
1223 uint32_t status = 0U;
1224 HAL_CAN_StateTypeDef state = hcan->State;
1225
1226 if ((state == HAL_CAN_STATE_READY) ||
1227 (state == HAL_CAN_STATE_LISTENING))
1228 {
1229 /* Check Sleep mode */
1230 if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
1231 {
1232 status = 1U;
1233 }
1234 }
1235
1236 /* Return function status */
1237 return status;
1238}
1239
1252HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, const CAN_TxHeaderTypeDef *pHeader,
1253 const uint8_t aData[], uint32_t *pTxMailbox)
1254{
1255 uint32_t transmitmailbox;
1256 HAL_CAN_StateTypeDef state = hcan->State;
1257 uint32_t tsr = READ_REG(hcan->Instance->TSR);
1258
1259 /* Check the parameters */
1260 assert_param(IS_CAN_IDTYPE(pHeader->IDE));
1261 assert_param(IS_CAN_RTR(pHeader->RTR));
1262 assert_param(IS_CAN_DLC(pHeader->DLC));
1263 if (pHeader->IDE == CAN_ID_STD)
1264 {
1265 assert_param(IS_CAN_STDID(pHeader->StdId));
1266 }
1267 else
1268 {
1269 assert_param(IS_CAN_EXTID(pHeader->ExtId));
1270 }
1271 assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
1272
1273 if ((state == HAL_CAN_STATE_READY) ||
1274 (state == HAL_CAN_STATE_LISTENING))
1275 {
1276 /* Check that all the Tx mailboxes are not full */
1277 if (((tsr & CAN_TSR_TME0) != 0U) ||
1278 ((tsr & CAN_TSR_TME1) != 0U) ||
1279 ((tsr & CAN_TSR_TME2) != 0U))
1280 {
1281 /* Select an empty transmit mailbox */
1282 transmitmailbox = (tsr & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
1283
1284 /* Store the Tx mailbox */
1285 *pTxMailbox = (uint32_t)1 << transmitmailbox;
1286
1287 /* Set up the Id */
1288 if (pHeader->IDE == CAN_ID_STD)
1289 {
1290 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
1291 pHeader->RTR);
1292 }
1293 else
1294 {
1295 hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
1296 pHeader->IDE |
1297 pHeader->RTR);
1298 }
1299
1300 /* Set up the DLC */
1301 hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
1302
1303 /* Set up the Transmit Global Time mode */
1304 if (pHeader->TransmitGlobalTime == ENABLE)
1305 {
1306 SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
1307 }
1308
1309 /* Set up the data field */
1310 WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
1311 ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
1312 ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
1313 ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
1314 ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
1315 WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
1316 ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) |
1317 ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
1318 ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
1319 ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
1320
1321 /* Request transmission */
1322 SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
1323
1324 /* Return function status */
1325 return HAL_OK;
1326 }
1327 else
1328 {
1329 /* Update error code */
1330 hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
1331
1332 return HAL_ERROR;
1333 }
1334 }
1335 else
1336 {
1337 /* Update error code */
1338 hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
1339
1340 return HAL_ERROR;
1341 }
1342}
1343
1352HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
1353{
1354 HAL_CAN_StateTypeDef state = hcan->State;
1355
1356 /* Check function parameters */
1357 assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
1358
1359 if ((state == HAL_CAN_STATE_READY) ||
1360 (state == HAL_CAN_STATE_LISTENING))
1361 {
1362 /* Check Tx Mailbox 0 */
1363 if ((TxMailboxes & CAN_TX_MAILBOX0) != 0U)
1364 {
1365 /* Add cancellation request for Tx Mailbox 0 */
1366 SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0);
1367 }
1368
1369 /* Check Tx Mailbox 1 */
1370 if ((TxMailboxes & CAN_TX_MAILBOX1) != 0U)
1371 {
1372 /* Add cancellation request for Tx Mailbox 1 */
1373 SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1);
1374 }
1375
1376 /* Check Tx Mailbox 2 */
1377 if ((TxMailboxes & CAN_TX_MAILBOX2) != 0U)
1378 {
1379 /* Add cancellation request for Tx Mailbox 2 */
1380 SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2);
1381 }
1382
1383 /* Return function status */
1384 return HAL_OK;
1385 }
1386 else
1387 {
1388 /* Update error code */
1389 hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
1390
1391 return HAL_ERROR;
1392 }
1393}
1394
1401uint32_t HAL_CAN_GetTxMailboxesFreeLevel(const CAN_HandleTypeDef *hcan)
1402{
1403 uint32_t freelevel = 0U;
1404 HAL_CAN_StateTypeDef state = hcan->State;
1405
1406 if ((state == HAL_CAN_STATE_READY) ||
1407 (state == HAL_CAN_STATE_LISTENING))
1408 {
1409 /* Check Tx Mailbox 0 status */
1410 if ((hcan->Instance->TSR & CAN_TSR_TME0) != 0U)
1411 {
1412 freelevel++;
1413 }
1414
1415 /* Check Tx Mailbox 1 status */
1416 if ((hcan->Instance->TSR & CAN_TSR_TME1) != 0U)
1417 {
1418 freelevel++;
1419 }
1420
1421 /* Check Tx Mailbox 2 status */
1422 if ((hcan->Instance->TSR & CAN_TSR_TME2) != 0U)
1423 {
1424 freelevel++;
1425 }
1426 }
1427
1428 /* Return Tx Mailboxes free level */
1429 return freelevel;
1430}
1431
1444uint32_t HAL_CAN_IsTxMessagePending(const CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
1445{
1446 uint32_t status = 0U;
1447 HAL_CAN_StateTypeDef state = hcan->State;
1448
1449 /* Check function parameters */
1450 assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
1451
1452 if ((state == HAL_CAN_STATE_READY) ||
1453 (state == HAL_CAN_STATE_LISTENING))
1454 {
1455 /* Check pending transmission request on the selected Tx Mailboxes */
1456 if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos))
1457 {
1458 status = 1U;
1459 }
1460 }
1461
1462 /* Return status */
1463 return status;
1464}
1465
1476uint32_t HAL_CAN_GetTxTimestamp(const CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
1477{
1478 uint32_t timestamp = 0U;
1479 uint32_t transmitmailbox;
1480 HAL_CAN_StateTypeDef state = hcan->State;
1481
1482 /* Check function parameters */
1483 assert_param(IS_CAN_TX_MAILBOX(TxMailbox));
1484
1485 if ((state == HAL_CAN_STATE_READY) ||
1486 (state == HAL_CAN_STATE_LISTENING))
1487 {
1488 /* Select the Tx mailbox */
1489 transmitmailbox = POSITION_VAL(TxMailbox);
1490
1491 /* Get timestamp */
1492 timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos;
1493 }
1494
1495 /* Return the timestamp */
1496 return timestamp;
1497}
1498
1510HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo,
1511 CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
1512{
1513 HAL_CAN_StateTypeDef state = hcan->State;
1514
1515 assert_param(IS_CAN_RX_FIFO(RxFifo));
1516
1517 if ((state == HAL_CAN_STATE_READY) ||
1518 (state == HAL_CAN_STATE_LISTENING))
1519 {
1520 /* Check the Rx FIFO */
1521 if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
1522 {
1523 /* Check that the Rx FIFO 0 is not empty */
1524 if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == 0U)
1525 {
1526 /* Update error code */
1527 hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
1528
1529 return HAL_ERROR;
1530 }
1531 }
1532 else /* Rx element is assigned to Rx FIFO 1 */
1533 {
1534 /* Check that the Rx FIFO 1 is not empty */
1535 if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == 0U)
1536 {
1537 /* Update error code */
1538 hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
1539
1540 return HAL_ERROR;
1541 }
1542 }
1543
1544 /* Get the header */
1545 pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
1546 if (pHeader->IDE == CAN_ID_STD)
1547 {
1548 pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
1549 }
1550 else
1551 {
1552 pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) &
1553 hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
1554 }
1555 pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR);
1556 if (((CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos) >= 8U)
1557 {
1558 /* Truncate DLC to 8 if received field is over range */
1559 pHeader->DLC = 8U;
1560 }
1561 else
1562 {
1563 pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
1564 }
1565 pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
1566 pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
1567
1568 /* Get the data */
1569 aData[0] = (uint8_t)((CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos);
1570 aData[1] = (uint8_t)((CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos);
1571 aData[2] = (uint8_t)((CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos);
1572 aData[3] = (uint8_t)((CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos);
1573 aData[4] = (uint8_t)((CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos);
1574 aData[5] = (uint8_t)((CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos);
1575 aData[6] = (uint8_t)((CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos);
1576 aData[7] = (uint8_t)((CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos);
1577
1578 /* Release the FIFO */
1579 if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
1580 {
1581 /* Release RX FIFO 0 */
1582 hcan->Instance->RF0R = CAN_RF0R_RFOM0;
1583 }
1584 else /* Rx element is assigned to Rx FIFO 1 */
1585 {
1586 /* Release RX FIFO 1 */
1587 hcan->Instance->RF1R = CAN_RF1R_RFOM1;
1588 }
1589
1590 /* Return function status */
1591 return HAL_OK;
1592 }
1593 else
1594 {
1595 /* Update error code */
1596 hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
1597
1598 return HAL_ERROR;
1599 }
1600}
1601
1610uint32_t HAL_CAN_GetRxFifoFillLevel(const CAN_HandleTypeDef *hcan, uint32_t RxFifo)
1611{
1612 uint32_t filllevel = 0U;
1613 HAL_CAN_StateTypeDef state = hcan->State;
1614
1615 /* Check function parameters */
1616 assert_param(IS_CAN_RX_FIFO(RxFifo));
1617
1618 if ((state == HAL_CAN_STATE_READY) ||
1619 (state == HAL_CAN_STATE_LISTENING))
1620 {
1621 if (RxFifo == CAN_RX_FIFO0)
1622 {
1623 filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0;
1624 }
1625 else /* RxFifo == CAN_RX_FIFO1 */
1626 {
1627 filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1;
1628 }
1629 }
1630
1631 /* Return Rx FIFO fill level */
1632 return filllevel;
1633}
1634
1638
1654
1663HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
1664{
1665 HAL_CAN_StateTypeDef state = hcan->State;
1666
1667 /* Check function parameters */
1668 assert_param(IS_CAN_IT(ActiveITs));
1669
1670 if ((state == HAL_CAN_STATE_READY) ||
1671 (state == HAL_CAN_STATE_LISTENING))
1672 {
1673 /* Enable the selected interrupts */
1674 __HAL_CAN_ENABLE_IT(hcan, ActiveITs);
1675
1676 /* Return function status */
1677 return HAL_OK;
1678 }
1679 else
1680 {
1681 /* Update error code */
1682 hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
1683
1684 return HAL_ERROR;
1685 }
1686}
1687
1696HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs)
1697{
1698 HAL_CAN_StateTypeDef state = hcan->State;
1699
1700 /* Check function parameters */
1701 assert_param(IS_CAN_IT(InactiveITs));
1702
1703 if ((state == HAL_CAN_STATE_READY) ||
1704 (state == HAL_CAN_STATE_LISTENING))
1705 {
1706 /* Disable the selected interrupts */
1707 __HAL_CAN_DISABLE_IT(hcan, InactiveITs);
1708
1709 /* Return function status */
1710 return HAL_OK;
1711 }
1712 else
1713 {
1714 /* Update error code */
1715 hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
1716
1717 return HAL_ERROR;
1718 }
1719}
1720
1727void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
1728{
1729 uint32_t errorcode = HAL_CAN_ERROR_NONE;
1730 uint32_t interrupts = READ_REG(hcan->Instance->IER);
1731 uint32_t msrflags = READ_REG(hcan->Instance->MSR);
1732 uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
1733 uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
1734 uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
1735 uint32_t esrflags = READ_REG(hcan->Instance->ESR);
1736
1737 /* Transmit Mailbox empty interrupt management *****************************/
1738 if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != 0U)
1739 {
1740 /* Transmit Mailbox 0 management *****************************************/
1741 if ((tsrflags & CAN_TSR_RQCP0) != 0U)
1742 {
1743 /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
1744 __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
1745
1746 if ((tsrflags & CAN_TSR_TXOK0) != 0U)
1747 {
1748 /* Transmission Mailbox 0 complete callback */
1749#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
1750 /* Call registered callback*/
1751 hcan->TxMailbox0CompleteCallback(hcan);
1752#else
1753 /* Call weak (surcharged) callback */
1754 HAL_CAN_TxMailbox0CompleteCallback(hcan);
1755#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
1756 }
1757 else
1758 {
1759 if ((tsrflags & CAN_TSR_ALST0) != 0U)
1760 {
1761 /* Update error code */
1762 errorcode |= HAL_CAN_ERROR_TX_ALST0;
1763 }
1764 else if ((tsrflags & CAN_TSR_TERR0) != 0U)
1765 {
1766 /* Update error code */
1767 errorcode |= HAL_CAN_ERROR_TX_TERR0;
1768 }
1769 else
1770 {
1771 /* Transmission Mailbox 0 abort callback */
1772#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
1773 /* Call registered callback*/
1774 hcan->TxMailbox0AbortCallback(hcan);
1775#else
1776 /* Call weak (surcharged) callback */
1777 HAL_CAN_TxMailbox0AbortCallback(hcan);
1778#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
1779 }
1780 }
1781 }
1782
1783 /* Transmit Mailbox 1 management *****************************************/
1784 if ((tsrflags & CAN_TSR_RQCP1) != 0U)
1785 {
1786 /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
1787 __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
1788
1789 if ((tsrflags & CAN_TSR_TXOK1) != 0U)
1790 {
1791 /* Transmission Mailbox 1 complete callback */
1792#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
1793 /* Call registered callback*/
1794 hcan->TxMailbox1CompleteCallback(hcan);
1795#else
1796 /* Call weak (surcharged) callback */
1797 HAL_CAN_TxMailbox1CompleteCallback(hcan);
1798#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
1799 }
1800 else
1801 {
1802 if ((tsrflags & CAN_TSR_ALST1) != 0U)
1803 {
1804 /* Update error code */
1805 errorcode |= HAL_CAN_ERROR_TX_ALST1;
1806 }
1807 else if ((tsrflags & CAN_TSR_TERR1) != 0U)
1808 {
1809 /* Update error code */
1810 errorcode |= HAL_CAN_ERROR_TX_TERR1;
1811 }
1812 else
1813 {
1814 /* Transmission Mailbox 1 abort callback */
1815#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
1816 /* Call registered callback*/
1817 hcan->TxMailbox1AbortCallback(hcan);
1818#else
1819 /* Call weak (surcharged) callback */
1820 HAL_CAN_TxMailbox1AbortCallback(hcan);
1821#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
1822 }
1823 }
1824 }
1825
1826 /* Transmit Mailbox 2 management *****************************************/
1827 if ((tsrflags & CAN_TSR_RQCP2) != 0U)
1828 {
1829 /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
1830 __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
1831
1832 if ((tsrflags & CAN_TSR_TXOK2) != 0U)
1833 {
1834 /* Transmission Mailbox 2 complete callback */
1835#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
1836 /* Call registered callback*/
1837 hcan->TxMailbox2CompleteCallback(hcan);
1838#else
1839 /* Call weak (surcharged) callback */
1840 HAL_CAN_TxMailbox2CompleteCallback(hcan);
1841#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
1842 }
1843 else
1844 {
1845 if ((tsrflags & CAN_TSR_ALST2) != 0U)
1846 {
1847 /* Update error code */
1848 errorcode |= HAL_CAN_ERROR_TX_ALST2;
1849 }
1850 else if ((tsrflags & CAN_TSR_TERR2) != 0U)
1851 {
1852 /* Update error code */
1853 errorcode |= HAL_CAN_ERROR_TX_TERR2;
1854 }
1855 else
1856 {
1857 /* Transmission Mailbox 2 abort callback */
1858#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
1859 /* Call registered callback*/
1860 hcan->TxMailbox2AbortCallback(hcan);
1861#else
1862 /* Call weak (surcharged) callback */
1863 HAL_CAN_TxMailbox2AbortCallback(hcan);
1864#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
1865 }
1866 }
1867 }
1868 }
1869
1870 /* Receive FIFO 0 overrun interrupt management *****************************/
1871 if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != 0U)
1872 {
1873 if ((rf0rflags & CAN_RF0R_FOVR0) != 0U)
1874 {
1875 /* Set CAN error code to Rx Fifo 0 overrun error */
1876 errorcode |= HAL_CAN_ERROR_RX_FOV0;
1877
1878 /* Clear FIFO0 Overrun Flag */
1879 __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
1880 }
1881 }
1882
1883 /* Receive FIFO 0 full interrupt management ********************************/
1884 if ((interrupts & CAN_IT_RX_FIFO0_FULL) != 0U)
1885 {
1886 if ((rf0rflags & CAN_RF0R_FULL0) != 0U)
1887 {
1888 /* Clear FIFO 0 full Flag */
1889 __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
1890
1891 /* Receive FIFO 0 full Callback */
1892#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
1893 /* Call registered callback*/
1894 hcan->RxFifo0FullCallback(hcan);
1895#else
1896 /* Call weak (surcharged) callback */
1897 HAL_CAN_RxFifo0FullCallback(hcan);
1898#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
1899 }
1900 }
1901
1902 /* Receive FIFO 0 message pending interrupt management *********************/
1903 if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != 0U)
1904 {
1905 /* Check if message is still pending */
1906 if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != 0U)
1907 {
1908 /* Receive FIFO 0 message pending Callback */
1909#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
1910 /* Call registered callback*/
1911 hcan->RxFifo0MsgPendingCallback(hcan);
1912#else
1913 /* Call weak (surcharged) callback */
1914 HAL_CAN_RxFifo0MsgPendingCallback(hcan);
1915#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
1916 }
1917 }
1918
1919 /* Receive FIFO 1 overrun interrupt management *****************************/
1920 if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != 0U)
1921 {
1922 if ((rf1rflags & CAN_RF1R_FOVR1) != 0U)
1923 {
1924 /* Set CAN error code to Rx Fifo 1 overrun error */
1925 errorcode |= HAL_CAN_ERROR_RX_FOV1;
1926
1927 /* Clear FIFO1 Overrun Flag */
1928 __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
1929 }
1930 }
1931
1932 /* Receive FIFO 1 full interrupt management ********************************/
1933 if ((interrupts & CAN_IT_RX_FIFO1_FULL) != 0U)
1934 {
1935 if ((rf1rflags & CAN_RF1R_FULL1) != 0U)
1936 {
1937 /* Clear FIFO 1 full Flag */
1938 __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
1939
1940 /* Receive FIFO 1 full Callback */
1941#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
1942 /* Call registered callback*/
1943 hcan->RxFifo1FullCallback(hcan);
1944#else
1945 /* Call weak (surcharged) callback */
1946 HAL_CAN_RxFifo1FullCallback(hcan);
1947#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
1948 }
1949 }
1950
1951 /* Receive FIFO 1 message pending interrupt management *********************/
1952 if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != 0U)
1953 {
1954 /* Check if message is still pending */
1955 if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != 0U)
1956 {
1957 /* Receive FIFO 1 message pending Callback */
1958#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
1959 /* Call registered callback*/
1960 hcan->RxFifo1MsgPendingCallback(hcan);
1961#else
1962 /* Call weak (surcharged) callback */
1963 HAL_CAN_RxFifo1MsgPendingCallback(hcan);
1964#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
1965 }
1966 }
1967
1968 /* Sleep interrupt management *********************************************/
1969 if ((interrupts & CAN_IT_SLEEP_ACK) != 0U)
1970 {
1971 if ((msrflags & CAN_MSR_SLAKI) != 0U)
1972 {
1973 /* Clear Sleep interrupt Flag */
1974 __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
1975
1976 /* Sleep Callback */
1977#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
1978 /* Call registered callback*/
1979 hcan->SleepCallback(hcan);
1980#else
1981 /* Call weak (surcharged) callback */
1982 HAL_CAN_SleepCallback(hcan);
1983#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
1984 }
1985 }
1986
1987 /* WakeUp interrupt management *********************************************/
1988 if ((interrupts & CAN_IT_WAKEUP) != 0U)
1989 {
1990 if ((msrflags & CAN_MSR_WKUI) != 0U)
1991 {
1992 /* Clear WakeUp Flag */
1993 __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
1994
1995 /* WakeUp Callback */
1996#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
1997 /* Call registered callback*/
1998 hcan->WakeUpFromRxMsgCallback(hcan);
1999#else
2000 /* Call weak (surcharged) callback */
2001 HAL_CAN_WakeUpFromRxMsgCallback(hcan);
2002#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
2003 }
2004 }
2005
2006 /* Error interrupts management *********************************************/
2007 if ((interrupts & CAN_IT_ERROR) != 0U)
2008 {
2009 if ((msrflags & CAN_MSR_ERRI) != 0U)
2010 {
2011 /* Check Error Warning Flag */
2012 if (((interrupts & CAN_IT_ERROR_WARNING) != 0U) &&
2013 ((esrflags & CAN_ESR_EWGF) != 0U))
2014 {
2015 /* Set CAN error code to Error Warning */
2016 errorcode |= HAL_CAN_ERROR_EWG;
2017
2018 /* No need for clear of Error Warning Flag as read-only */
2019 }
2020
2021 /* Check Error Passive Flag */
2022 if (((interrupts & CAN_IT_ERROR_PASSIVE) != 0U) &&
2023 ((esrflags & CAN_ESR_EPVF) != 0U))
2024 {
2025 /* Set CAN error code to Error Passive */
2026 errorcode |= HAL_CAN_ERROR_EPV;
2027
2028 /* No need for clear of Error Passive Flag as read-only */
2029 }
2030
2031 /* Check Bus-off Flag */
2032 if (((interrupts & CAN_IT_BUSOFF) != 0U) &&
2033 ((esrflags & CAN_ESR_BOFF) != 0U))
2034 {
2035 /* Set CAN error code to Bus-Off */
2036 errorcode |= HAL_CAN_ERROR_BOF;
2037
2038 /* No need for clear of Error Bus-Off as read-only */
2039 }
2040
2041 /* Check Last Error Code Flag */
2042 if (((interrupts & CAN_IT_LAST_ERROR_CODE) != 0U) &&
2043 ((esrflags & CAN_ESR_LEC) != 0U))
2044 {
2045 switch (esrflags & CAN_ESR_LEC)
2046 {
2047 case (CAN_ESR_LEC_0):
2048 /* Set CAN error code to Stuff error */
2049 errorcode |= HAL_CAN_ERROR_STF;
2050 break;
2051 case (CAN_ESR_LEC_1):
2052 /* Set CAN error code to Form error */
2053 errorcode |= HAL_CAN_ERROR_FOR;
2054 break;
2055 case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
2056 /* Set CAN error code to Acknowledgement error */
2057 errorcode |= HAL_CAN_ERROR_ACK;
2058 break;
2059 case (CAN_ESR_LEC_2):
2060 /* Set CAN error code to Bit recessive error */
2061 errorcode |= HAL_CAN_ERROR_BR;
2062 break;
2063 case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
2064 /* Set CAN error code to Bit Dominant error */
2065 errorcode |= HAL_CAN_ERROR_BD;
2066 break;
2067 case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
2068 /* Set CAN error code to CRC error */
2069 errorcode |= HAL_CAN_ERROR_CRC;
2070 break;
2071 default:
2072 break;
2073 }
2074
2075 /* Clear Last error code Flag */
2076 CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
2077 }
2078 }
2079
2080 /* Clear ERRI Flag */
2081 __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
2082 }
2083
2084 /* Call the Error call Back in case of Errors */
2085 if (errorcode != HAL_CAN_ERROR_NONE)
2086 {
2087 /* Update error code in handle */
2088 hcan->ErrorCode |= errorcode;
2089
2090 /* Call Error callback function */
2091#if USE_HAL_CAN_REGISTER_CALLBACKS == 1
2092 /* Call registered callback*/
2093 hcan->ErrorCallback(hcan);
2094#else
2095 /* Call weak (surcharged) callback */
2096 HAL_CAN_ErrorCallback(hcan);
2097#endif /* USE_HAL_CAN_REGISTER_CALLBACKS */
2098 }
2099}
2100
2104
2131
2138__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
2139{
2140 /* Prevent unused argument(s) compilation warning */
2141 UNUSED(hcan);
2142
2143 /* NOTE : This function Should not be modified, when the callback is needed,
2144 the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
2145 user file
2146 */
2147}
2148
2155__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
2156{
2157 /* Prevent unused argument(s) compilation warning */
2158 UNUSED(hcan);
2159
2160 /* NOTE : This function Should not be modified, when the callback is needed,
2161 the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
2162 user file
2163 */
2164}
2165
2172__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
2173{
2174 /* Prevent unused argument(s) compilation warning */
2175 UNUSED(hcan);
2176
2177 /* NOTE : This function Should not be modified, when the callback is needed,
2178 the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
2179 user file
2180 */
2181}
2182
2189__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
2190{
2191 /* Prevent unused argument(s) compilation warning */
2192 UNUSED(hcan);
2193
2194 /* NOTE : This function Should not be modified, when the callback is needed,
2195 the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
2196 user file
2197 */
2198}
2199
2206__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
2207{
2208 /* Prevent unused argument(s) compilation warning */
2209 UNUSED(hcan);
2210
2211 /* NOTE : This function Should not be modified, when the callback is needed,
2212 the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
2213 user file
2214 */
2215}
2216
2223__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
2224{
2225 /* Prevent unused argument(s) compilation warning */
2226 UNUSED(hcan);
2227
2228 /* NOTE : This function Should not be modified, when the callback is needed,
2229 the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
2230 user file
2231 */
2232}
2233
2240__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan)
2241{
2242 /* Prevent unused argument(s) compilation warning */
2243 UNUSED(hcan);
2244
2245 /* NOTE : This function Should not be modified, when the callback is needed,
2246 the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the
2247 user file
2248 */
2249}
2250
2257__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
2258{
2259 /* Prevent unused argument(s) compilation warning */
2260 UNUSED(hcan);
2261
2262 /* NOTE : This function Should not be modified, when the callback is needed,
2263 the HAL_CAN_RxFifo0FullCallback could be implemented in the user
2264 file
2265 */
2266}
2267
2274__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
2275{
2276 /* Prevent unused argument(s) compilation warning */
2277 UNUSED(hcan);
2278
2279 /* NOTE : This function Should not be modified, when the callback is needed,
2280 the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
2281 user file
2282 */
2283}
2284
2291__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
2292{
2293 /* Prevent unused argument(s) compilation warning */
2294 UNUSED(hcan);
2295
2296 /* NOTE : This function Should not be modified, when the callback is needed,
2297 the HAL_CAN_RxFifo1FullCallback could be implemented in the user
2298 file
2299 */
2300}
2301
2308__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
2309{
2310 /* Prevent unused argument(s) compilation warning */
2311 UNUSED(hcan);
2312
2313 /* NOTE : This function Should not be modified, when the callback is needed,
2314 the HAL_CAN_SleepCallback could be implemented in the user file
2315 */
2316}
2317
2324__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
2325{
2326 /* Prevent unused argument(s) compilation warning */
2327 UNUSED(hcan);
2328
2329 /* NOTE : This function Should not be modified, when the callback is needed,
2330 the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
2331 user file
2332 */
2333}
2334
2341__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
2342{
2343 /* Prevent unused argument(s) compilation warning */
2344 UNUSED(hcan);
2345
2346 /* NOTE : This function Should not be modified, when the callback is needed,
2347 the HAL_CAN_ErrorCallback could be implemented in the user file
2348 */
2349}
2350
2354
2371
2378HAL_CAN_StateTypeDef HAL_CAN_GetState(const CAN_HandleTypeDef *hcan)
2379{
2380 HAL_CAN_StateTypeDef state = hcan->State;
2381
2382 if ((state == HAL_CAN_STATE_READY) ||
2383 (state == HAL_CAN_STATE_LISTENING))
2384 {
2385 /* Check sleep mode acknowledge flag */
2386 if ((hcan->Instance->MSR & CAN_MSR_SLAK) != 0U)
2387 {
2388 /* Sleep mode is active */
2389 state = HAL_CAN_STATE_SLEEP_ACTIVE;
2390 }
2391 /* Check sleep mode request flag */
2392 else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != 0U)
2393 {
2394 /* Sleep mode request is pending */
2395 state = HAL_CAN_STATE_SLEEP_PENDING;
2396 }
2397 else
2398 {
2399 /* Neither sleep mode request nor sleep mode acknowledge */
2400 }
2401 }
2402
2403 /* Return CAN state */
2404 return state;
2405}
2406
2413uint32_t HAL_CAN_GetError(const CAN_HandleTypeDef *hcan)
2414{
2415 /* Return CAN error code */
2416 return hcan->ErrorCode;
2417}
2418
2425HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan)
2426{
2427 HAL_StatusTypeDef status = HAL_OK;
2428 HAL_CAN_StateTypeDef state = hcan->State;
2429
2430 if ((state == HAL_CAN_STATE_READY) ||
2431 (state == HAL_CAN_STATE_LISTENING))
2432 {
2433 /* Reset CAN error code */
2434 hcan->ErrorCode = 0U;
2435 }
2436 else
2437 {
2438 /* Update error code */
2439 hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
2440
2441 status = HAL_ERROR;
2442 }
2443
2444 /* Return the status */
2445 return status;
2446}
2447
2451
2455
2456#endif /* HAL_CAN_MODULE_ENABLED */
2457
2461
2462#endif /* CAN1 */
2463
HAL_GetTick
uint32_t HAL_GetTick(void)
Provides a tick value in millisecond.
Definition stm32f4xx_hal.c:323
assert_param
#define assert_param(expr)
Definition stm32_assert_template.h:46
stm32f4xx_hal.h
This file contains all the functions prototypes for the HAL module driver.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition stm32f4xx_hal_def.h:39
HAL_ERROR
@ HAL_ERROR
Definition stm32f4xx_hal_def.h:41
HAL_OK
@ HAL_OK
Definition stm32f4xx_hal_def.h:40