System Configuration functions. More...

Collaboration diagram for SYSTEM:

Functions
void	LL_SetSystemCoreClock (uint32_t HCLKFrequency)
	This function sets directly SystemCoreClock CMSIS variable.
ErrorStatus	LL_SetFlashLatency (uint32_t HCLK_Frequency)
	Update number of Flash wait states in line with new frequency and current voltage range.
ErrorStatus	LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct)
	This function configures system clock at maximum frequency with HSI as clock source of the PLL.
ErrorStatus	LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct)
	This function configures system clock with HSE as clock source of the PLL.

Detailed Description

System Configuration functions.

===============================================================================
          ##### System Configuration functions #####
===============================================================================
   [..]
        System, AHB and APB buses clocks configuration

        (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 180000000 Hz.

Function Documentation

◆ LL_PLL_ConfigSystemClock_HSE()

ErrorStatus LL_PLL_ConfigSystemClock_HSE	(	uint32_t	HSEFrequency,
		uint32_t	HSEBypass,
		LL_UTILS_PLLInitTypeDef *	UTILS_PLLInitStruct,
		LL_UTILS_ClkInitTypeDef *	UTILS_ClkInitStruct )

This function configures system clock with HSE as clock source of the PLL.

Note

The application need to ensure that PLL is disabled.

PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
PLLM: ensure that the VCO input frequency ranges from RCC_PLLVCO_INPUT_MIN to RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
PLLN: ensure that the VCO output frequency is between RCC_PLLVCO_OUTPUT_MIN and RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)

Parameters

HSEFrequency	Value between Min_Data = 4000000 and Max_Data = 26000000
HSEBypass	This parameter can be one of the following values: LL_UTILS_HSEBYPASS_ON LL_UTILS_HSEBYPASS_OFF
UTILS_PLLInitStruct	pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct	pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.

Return values

An	ErrorStatus enumeration value: SUCCESS: Max frequency configuration done ERROR: Max frequency configuration not done

< HSE Bypass is enabled

Definition at line 540 of file stm32f4xx_ll_utils.c.

References assert_param, IS_LL_UTILS_HSE_BYPASS, IS_LL_UTILS_HSE_FREQUENCY, LL_UTILS_HSEBYPASS_ON, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLP, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

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◆ LL_PLL_ConfigSystemClock_HSI()

ErrorStatus LL_PLL_ConfigSystemClock_HSI	(	LL_UTILS_PLLInitTypeDef *	UTILS_PLLInitStruct,
		LL_UTILS_ClkInitTypeDef *	UTILS_ClkInitStruct )

This function configures system clock at maximum frequency with HSI as clock source of the PLL.

Note

The application need to ensure that PLL is disabled.

Function is based on the following formula:

PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLP)
PLLM: ensure that the VCO input frequency ranges from RCC_PLLVCO_INPUT_MIN to RCC_PLLVCO_INPUT_MAX (PLLVCO_input = HSI frequency / PLLM)
PLLN: ensure that the VCO output frequency is between RCC_PLLVCO_OUTPUT_MIN and RCC_PLLVCO_OUTPUT_MAX (PLLVCO_output = PLLVCO_input * PLLN)
PLLP: ensure that max frequency at 180000000 Hz is reach (PLLVCO_output / PLLP)

Parameters

UTILS_PLLInitStruct	pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct	pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.

Return values

An	ErrorStatus enumeration value: SUCCESS: Max frequency configuration done ERROR: Max frequency configuration not done

Definition at line 483 of file stm32f4xx_ll_utils.c.

References HSI_VALUE, LL_UTILS_PLLInitTypeDef::PLLM, LL_UTILS_PLLInitTypeDef::PLLN, LL_UTILS_PLLInitTypeDef::PLLP, UTILS_EnablePLLAndSwitchSystem(), UTILS_GetPLLOutputFrequency(), and UTILS_PLL_IsBusy().

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◆ LL_SetFlashLatency()

ErrorStatus LL_SetFlashLatency ( uint32_t HCLK_Frequency )

Update number of Flash wait states in line with new frequency and current voltage range.

Note: This Function support ONLY devices with supply voltage (voltage range) between 2.7V and 3.6V

Parameters

HCLK_Frequency HCLK frequency

Return values

An	ErrorStatus enumeration value: SUCCESS: Latency has been modified ERROR: Latency cannot be modified

< HCLK frequency to set FLASH latency 2 in power scale 2

< HCLK frequency to set FLASH latency 1 in power scale 2

Definition at line 338 of file stm32f4xx_ll_utils.c.

References UTILS_SCALE2_LATENCY1_FREQ, and UTILS_SCALE2_LATENCY2_FREQ.

Referenced by UTILS_EnablePLLAndSwitchSystem().

◆ LL_SetSystemCoreClock()

void LL_SetSystemCoreClock ( uint32_t HCLKFrequency )

This function sets directly SystemCoreClock CMSIS variable.

Note: Variable can be calculated also through SystemCoreClockUpdate function.

Parameters

HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)

Return values

None

Definition at line 323 of file stm32f4xx_ll_utils.c.

Referenced by UTILS_EnablePLLAndSwitchSystem().

Functions

Detailed Description

Function Documentation

◆ LL_PLL_ConfigSystemClock_HSE()

◆ LL_PLL_ConfigSystemClock_HSI()

◆ LL_SetFlashLatency()

◆ LL_SetSystemCoreClock()