Collaboration diagram for RCCEx Exported Macros:

Macros
#define	__HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)
	Macro to configure the main PLL clock source, multiplication and division factors.
#define	__HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__)
	Macro to configure the PLLI2S clock multiplication and division factors .

Detailed Description

Macro Definition Documentation

◆ __HAL_RCC_PLL_CONFIG

#define __HAL_RCC_PLL_CONFIG	(	__RCC_PLLSource__,
		__PLLM__,
		__PLLN__,
		__PLLP__,
		__PLLQ__ )

Value:

(RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \
                 ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos)                | \
                 ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos)    | \
                 ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))

Macro to configure the main PLL clock source, multiplication and division factors.

Note: This function must be used only when the main PLL is disabled.

Parameters

__RCC_PLLSource__

specifies the PLL entry clock source. This parameter can be one of the following values:

RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

Note: This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.

Parameters

__PLLM__ specifies the division factor for PLL VCO input clock This parameter must be a number between Min_Data = 2 and Max_Data = 63.

Note: You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 2 MHz. It is recommended to select a frequency of 2 MHz to limit PLL jitter.

Parameters

__PLLN__ specifies the multiplication factor for PLL VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432 Except for STM32F411xE devices where Min_Data = 192.

Note: You have to set the PLLN parameter correctly to ensure that the VCO output frequency is between 100 and 432 MHz, Except for STM32F411xE devices where frequency is between 192 and 432 MHz.

Parameters

__PLLP__	specifies the division factor for main system clock (SYSCLK) This parameter must be a number in the range {2, 4, 6, or 8}.
__PLLQ__	specifies the division factor for OTG FS, SDIO and RNG clocks This parameter must be a number between Min_Data = 2 and Max_Data = 15.

Note: If the USB OTG FS is used in your application, you have to set the PLLQ parameter correctly to have 48 MHz clock for the USB. However, the SDIO and RNG need a frequency lower than or equal to 48 MHz to work correctly.

Definition at line 5870 of file stm32f4xx_hal_rcc_ex.h.

◆ __HAL_RCC_PLLI2S_CONFIG

#define __HAL_RCC_PLLI2S_CONFIG	(		__PLLI2SN__,
			__PLLI2SR__ )

Value:

(RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\

((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))

Macro to configure the PLLI2S clock multiplication and division factors .

Note: This macro must be used only when the PLLI2S is disabled.; PLLI2S clock source is common with the main PLL (configured in HAL_RCC_ClockConfig() API).

Parameters

__PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock This parameter must be a number between Min_Data = 50 and Max_Data = 432.

Note: You have to set the PLLI2SN parameter correctly to ensure that the VCO output frequency is between Min_Data = 100 and Max_Data = 432 MHz.

Parameters

__PLLI2SR__ specifies the division factor for I2S clock This parameter must be a number between Min_Data = 2 and Max_Data = 7.

Note: You have to set the PLLI2SR parameter correctly to not exceed 192 MHz on the I2S clock frequency.

Definition at line 5974 of file stm32f4xx_hal_rcc_ex.h.